公开(公告)号：US06835666B2

公开(公告)日：2004-12-28

申请号：US10291070

申请日：2002-11-08

申请人： Martin Popp

发明人： Martin Popp

IPC分类号： H01L21302

CPC分类号： H01L21/3086

摘要： A mask is fabricated by applying a sacrificial layer on a semiconductor wafer. The sacrificial layer is then processed with the aid of a first and a second lithographic process sequence in order to pattern the sacrificial layer in a first and a second direction. A hard mask layer is subsequently applied in order to completely enclose the patterned sacrificial layer. Finally, the sacrificial layer is then removed from the hard mask layer.

摘要翻译： 通过在半导体晶片上施加牺牲层来制造掩模。 然后借助于第一和第二光刻工艺顺序处理牺牲层，以便沿第一和第二方向图案化牺牲层。 随后施加硬掩模层以完全包围图案化的牺牲层。 最后，从硬掩模层去除牺牲层。

公开(公告)号：US06835665B2

公开(公告)日：2004-12-28

申请号：US10090761

申请日：2002-03-06

申请人： Nobuyuki Mise ,  Ken Yoshioka ,  Ryoji Nishio ,  Tatehito Usui

发明人： Nobuyuki Mise ,  Ken Yoshioka ,  Ryoji Nishio ,  Tatehito Usui

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  C23F4/00 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31691 ,  H01L21/32139 ,  H01L28/65 ,  H01L43/12

摘要： A film of hardly-etched material formed on a substrate is etched using a mask formed on the film of hardly-etched material and a plasma, wherein the film of hardly-etched material is etched using the mask formed with a side wall angled at 90 degrees or less with respect to the surface of the substrate, thereby forming the etched film with a taper angle to the surface of the substrate equal to or larger than the taper angle of the mask.

摘要翻译： 使用形成在难蚀刻材料和等离子体的膜上的掩模蚀刻在基板上形成的几乎蚀刻的材料的膜，其中使用形成有角度为90°的侧壁的掩模蚀刻难蚀刻材料的膜 度以下，由此形成与基板的表面成锥角的蚀刻膜等于或大于掩模的锥角。

公开(公告)号：US06830939B2

公开(公告)日：2004-12-14

申请号：US10232987

申请日：2002-08-28

申请人： Kenneth C. Harvey ,  Jimmy W. Hosch ,  Neal B. Gallagher ,  Barry M. Wise

发明人： Kenneth C. Harvey ,  Jimmy W. Hosch ,  Neal B. Gallagher ,  Barry M. Wise

IPC分类号： H01L21302

CPC分类号： H01J37/32935 ,  G01N21/73 ,  H01J37/32963

摘要： The present invention is directed to a system, method and software product for creating a predictive model of the endpoint of etch processes using Partial Least Squares Discriminant Analysis (PLS-DA). Calibration data is collected from a calibration wafer using optical emission spectroscopy (OES). The data may be non-periodic or periodic with time and periodic signals may be sampled synchronously or non-synchronously. The OES data is arranged in a spectra matrix X having one row for each data sample. The OES data is processed depending upon whether or not it is synchronous. Synchronous data is arranged in an unfolded spectra matrix X having one row for each period of data samples. A previewed endpoint signal is plotted using wavelengths known to exhibit good endpoint characteristics. Regions of stable intensity values in the endpoint plot that are associated with either the etch region or the post-etch region are identified by sample number. An X-block is created from the processed OES data samples associated with the two regions of stable intensity values. Non-periodic OES data and asynchronously sampled periodic OES data are arranged in a X-block by one sample per row. Synchronously sampled periodic OES data are arranged in the X-block by one period per row. A y-block is created by assigning a discriminate variable value of “1” to OES samples associated with the class, i.e. the etch, and assigning a discriminate value of “0” to all samples not in the class, i.e. the post-etch. A b-vector is regressed from the X- and y-blocks using PLS and is used with the appropriate algorithm for processing real-time OES data from a production etch process for detecting an endpoint.

公开(公告)号：US06828241B2

公开(公告)日：2004-12-07

申请号：US10041838

申请日：2002-01-07

申请人： Arnold V. Kholodenko ,  Peter Porshnev

发明人： Arnold V. Kholodenko ,  Peter Porshnev

IPC分类号： H01L21302

CPC分类号： H01J37/32862 ,  B08B7/0035 ,  C23C14/564 ,  C23C16/4405 ,  H01J37/321

摘要： An electro-negative cleaning or etchant gas, such as fluorine, that was ionized from a stable supply gas such as NH3 in a secondary chamber and recombined in the primary chamber, is re-ionized within the primary chamber by electron attachment by ionizing an electron donor gas, such as helium, in the primary chamber.

摘要翻译： 在次级室中从稳定的供应气体例如NH 3离子化并在初级室中重新组合的电负性清洁或蚀刻剂气体，例如氟，通过电子附着电离电离在主室内 供体气体，如氦气，在主室中。

公开(公告)号：US06821905B2

公开(公告)日：2004-11-23

申请号：US10209466

申请日：2002-07-30

申请人： Shing-Chyang Pan ,  Shwang-Ming Jeng ,  Chen-Hua Yu ,  Grace H. Ho

发明人： Shing-Chyang Pan ,  Shwang-Ming Jeng ,  Chen-Hua Yu ,  Grace H. Ho

IPC分类号： H01L21302

CPC分类号： H01L21/76826 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76807

摘要： A method for preventing carbon and nitrogen penetration from a deposited overlayer into a dielectric insulating layer to improve a subsequent photolithographic patterning and anisotropic etching process including providing a semiconductor wafer having a process surface including an exposed dielectric insulating layer; and, subjecting the dielectric insulating layer to a hydrogen containing plasma treatment to form a penetration resistance to one of nitrogen containing and carbon containing species.

公开(公告)号：US06815367B2

公开(公告)日：2004-11-09

申请号：US10114484

申请日：2002-04-03

申请人： Xiaochun Linda Chen

发明人： Xiaochun Linda Chen

IPC分类号： H01L21302

CPC分类号： H01L21/0332 ,  G03F7/091

摘要： A process of eliminating resist footing on a hardmask when preparing a semiconductor wafer stack, comprising: a) depositing a layer of hardmask material on a substrate; b) subjecting the hardmask to oxygen under conditions sufficient to produce an oxide cap layer and provide a hardmask/oxide cap layer with a substrate reflectivity below 0.8%; c) forming a layer of SiO2 on the hardmask/oxide cap layer; d) forming a layer of photoresist on the layer of SiO2; e) patterning and developing the layer of photoresist by exposing photoresist; and f) etching exposed portions of the layer of hardmask/oxide cap layer/SiO2 layer to obtain a semiconductor wafer stack with no standing waves and free from resist footing.

公开(公告)号：US06815355B2

公开(公告)日：2004-11-09

申请号：US10267206

申请日：2002-10-09

申请人： Elgin Quek

发明人： Elgin Quek

IPC分类号： H01L21302

CPC分类号： H01L29/66598 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656

摘要： A process for fabricating a complimentary metal oxide semiconductor (CMOS), device featuring composite insulator spacer shapes which allow P channel (PMOS), short channel effects to be minimized, and allow reductions in resistance for N channel (NMOS), source/drain extension regions to be realized, has been developed. The process features initial composite insulator spacers formed in the sides of gate structures after definition of the NMOS and PMOS source/drain extension regions. The initial composite insulator spacer, comprised of an underlying silicon oxide component, an L-shaped silicon nitride component, and an overlying doped oxide component, is then used for definition of the PMOS heavily doped source/drain region, allowing for adequate space between the heavily doped source/drain and channel regions, thus reducing the risk of short channel effects. After removal of the doped oxide component, the L-shaped composite insulator spacer is used to define, via ion implantation procedures, an NMOS heavily doped region, featuring a portion of the heavily doped source/drain region formed underlying a horizontal feature of the L-shaped silicon nitride component, therefore compensating a portion of the NMOS source/drain extension region, and resulting in the desired reduction in source/drain resistance.

摘要翻译： 用于制造互补金属氧化物半导体（CMOS）的器件，其特征在于复合绝缘体间隔物形状，其允许P沟道（PMOS），短沟道效应被最小化，并且允许降低N沟道（NMOS）的电阻/源极/漏极扩展 要实现的地区，已经开发。 该工艺的特征在于限定NMOS和PMOS源极/漏极延伸区域之后，在栅极结构的侧面形成初始复合绝缘体间隔物。 然后，使用包括下面的氧化硅组分，L型氮化硅组分和上覆的掺杂氧化物组分的初始复合绝缘体间隔物来定义PMOS重掺杂源极/漏极区域，从而允许在 重掺杂的源极/漏极和沟道区域，从而降低短沟道效应的风险。 在去除掺杂的氧化物组分之后，使用L形复合绝缘体间隔物来经由离子注入工艺来定义NMOS重掺杂区域，其特征在于在L的水平特征下形成的重掺杂源极/漏极区的一部分 形状的氮化硅部件，因此补偿NMOS源极/漏极延伸区域的一部分，并导致所需的源极/漏极电阻的降低。

公开(公告)号：US06809039B2

公开(公告)日：2004-10-26

申请号：US09940247

申请日：2001-08-27

申请人： Takamasa Ito

发明人： Takamasa Ito

IPC分类号： H01L21302

CPC分类号： C23F1/28 ,  H01L21/28518 ,  H01L21/32134

摘要： A method for forming a metal silicide layer in a self-aligned manner on a source region and a drain region and a gate electrode of a semiconductor device formed on a semiconductor substrate, the method comprising the steps of: depositing a cobalt film over an entire surface of the semiconductor device formed on the semiconductor substrate, forming the metal silicide layer on the source region and drain region and the gate electrode by performing a heat treating thereof, and etching away an unreacted cobalt remaining on the semiconductor substrate using an admixture solution made of hydrochloric acid, hydrogen peroxide, and water, having relative concentration ratio ranging from 1:1:5 to 3:1:5, at a solution temperature of 25 to 45° C., with an etching time of 1 to 20 minutes.

摘要翻译： 一种在半导体衬底上形成的半导体器件的源极区和漏极区以及栅电极上以自对准的方式形成金属硅化物层的方法，该方法包括以下步骤： 形成在半导体衬底上的半导体器件的表面，通过进行其热处理在源极区和漏极区以及栅电极上形成金属硅化物层，并使用制备的混合溶液蚀刻残留在半导体衬底上的未反应的钴 的盐酸，过氧化氢和水，相对浓度比为1:1:5〜3:1:5，溶液温度为25〜45℃，蚀刻时间为1〜20分钟。

公开(公告)号：US06809031B1

公开(公告)日：2004-10-26

申请号：US09752610

申请日：2000-12-27

申请人： Michael S. Lacy

发明人： Michael S. Lacy

IPC分类号： H01L21302

CPC分类号： H01L22/34 ,  H01L21/31051

摘要： In a method for manufacturing a test pattern wafer, a silicon substrate is provided. A sacrificial oxide layer is deposited over the silicon substrate, and simulated transistor structure test features are fabricated into and on the sacrificial oxide layer. Chemical mechanical polishing characterization is performed using the test pattern wafer which provides data for the characterization of the chemical mechanical polishing. The sacrificial oxide layer is then stripped along with the simulated transistor structure test features, allowing the silicon substrate to be reclaimed and to be used in the fabrication of subsequent test pattern wafers.

摘要翻译： 在制造测试图案晶片的方法中，提供硅衬底。 在硅衬底上沉积牺牲氧化物层，并且将模拟的晶体管结构测试特征制造在牺牲氧化物层中和上。 使用提供化学机械抛光表征的数据的测试图案晶片进行化学机械抛光表征。 然后将牺牲氧化物层与模拟的晶体管结构测试特征一起剥离，允许回收硅衬底并用于后续测试图案晶片的制造。

公开(公告)号：US06806204B1

公开(公告)日：2004-10-19

申请号：US10611837

申请日：2003-06-30

申请人： Jun-Fei Zheng ,  Jesper Hanberg

发明人： Jun-Fei Zheng ,  Jesper Hanberg

IPC分类号： H01L21302

CPC分类号： H01L21/3081 ,  H01L21/30612

摘要： In accordance with embodiments of the methods of the present invention, a sacrificial layer provides an etch speed modification to effectively etch multiple semiconductor devices having dissimilar materials to a common layer or substrate with a common etch process. The time to etch remove a second exposed portion is compared with the time to etch remove a first exposed portion, and a sacrificial layer is deposited on the first exposed portion having a time to etch remove substantially equal to the difference. The sacrificial layer is provided to have predetermined material composition, material property and layer thickness, among other things, to provide a desired time to etch remove. The methods also provide for self-aligned via formation providing highly defined vias by the etch removal of sacrificial material rather than direct etching of the vie. The methods also provide planarization between two or more devices.

摘要翻译： 根据本发明的方法的实施例，牺牲层提供蚀刻速度修改以通过公共蚀刻工艺有效地将具有不同材料的多个半导体器件蚀刻到公共层或衬底。 将蚀刻去除第二暴露部分的时间与蚀刻时间相比较去除第一暴露部分，并且牺牲层沉积在第一暴露部分上，其蚀刻时间基本上等于该差异。 提供牺牲层以具有预定的材料组成，材料性质和层厚度，以提供蚀刻去除所需的时间。 这些方法还提供了自对准通孔形成，通过蚀刻去除牺牲材料而不是直接蚀刻，提供高度限定的通孔。 这些方法还提供两个或多个设备之间的平坦化。