Invention Grant
- Patent Title: Method of reducing RIE lag for deep trench silicon etching
- Patent Title (中): 减少深沟槽硅蚀刻RIE滞后的方法
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Application No.: US09583963Application Date: 2000-05-31
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Publication No.: US06284666B1Publication Date: 2001-09-04
- Inventor: Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
- Applicant: Munir D. Naeem , Gangadhara S. Mathad , Byeong Yeol Kim , Stephan P. Kudelka , Brian S. Lee , Heon Lee , Elizabeth Morales , Young-Jin Park , Rajiv M. Ranade
- Main IPC: H01L21302
- IPC: H01L21302

Abstract:
A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e.,
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