A chip arrangement (1) has a substrate board (2) with an opening (3), into which a carrier chip (4) is inserted, which has an electrical or electronic structural component (5). At least one conductor path (7) is integrated into the carrier chip (4), which connects the structural component (5) to the electrical connection contact (8). The carrier chip (4) is inserted into the opening (3) in such a way that its ends project beyond the opposite-facing, flat-sided surfaces (9, 9′) of the substrate board (2), and thereby form overhangs (10, 10′). Here, the structural component is arranged on the overhang (10) projecting beyond the one surface (9), and the connection contact (8) is arranged on the overhang (10′) projecting beyond the other surface (9′), and the conductor path (7) connecting the structural component (5) and the connection contact (8) passes through the opening (3). A seal is arranged between the substrate board (2) and the carrier chip (4).