A memory chip is comprises memory cells and, for example, 16 amplifiers, each having a first output terminal and a second output terminal. The 16 amplifiers are connected at the first output terminal to 16 first-type signal lines RD(0) to RD(15) and at the second output terminal to four second-type signal lines bTRD(0) to bTRD(3) in increment fashion. More precisely, the second output terminals of every four amplifiers are connected the four second-type signal lines, respectively. A coincidence/non-coincidence determining circuit determines how the potentials of the second-type signal lines bTRD(0) to bTRD(3) and the potentials of the first-type signal lines RD(0) to RD(15) connected to all amplifiers that are connected to the second-type signal lines change when all data items of the same polarity are read from memory cells. Hence, a compressed-data test can be performed thereby compressing 16-bit data into 4-bit data by using only 20 signal lines.