发明授权
US06310491B1 Sequential logic circuit with active and sleep modes 失效
具有主动和睡眠模式的顺序逻辑电路

  • 专利标题: Sequential logic circuit with active and sleep modes
  • 专利标题(中): 具有主动和睡眠模式的顺序逻辑电路
  • 申请号: US09411834
    申请日: 1999-10-04
  • 公开(公告)号: US06310491B1
    公开(公告)日: 2001-10-30
  • 发明人: Tadahiko Ogawa
  • 申请人: Tadahiko Ogawa
  • 优先权: JP10-280767 19981002
  • 主分类号: H03K19173
  • IPC分类号: H03K19173
Sequential logic circuit with active and sleep modes
摘要:
A sequential logic circuit having active and sleep modes prevents stored information from being lost immediately after the transition from a sleep mode to an active mode. This sequential logic circuit includes a latch circuit having an input terminal to which an input signal is applied, an output terminal from which and output signal is derived, and a set and/or reset terminal to which a set and/or reset signal is applied. The latch circuit has an active mode where a latch function is operable and a sleep mode where the latch function is inoperable, one of which is alternatively selected. The output signal is set or reset to have a specific logic state by the set or reset signal having a specific logic level applied to the set or reset terminal in the active mode. The sequential logic circuit further includes circuitry for preventing the set or reset signal from being applied to the set or reset terminal in the sleep mode, thereby avoiding loss of information or data latched in the latch circuit prior to transition to the sleep mode from the active mode. Thus, the information-latch operation in both of the modes is ensured.
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