公开(公告)号：US06836145B2

公开(公告)日：2004-12-28

申请号：US10165666

申请日：2002-06-06

申请人： Richard A. Mecier ,  Charles L. Ingalls

发明人： Richard A. Mecier ,  Charles L. Ingalls

IPC分类号： H03K19173

CPC分类号： G11C17/18 ,  G11C5/145 ,  G11C11/4074 ,  H02M3/073 ,  H03K17/063

摘要： An isolation circuit for coupling a large programming voltage from an external terminal to a circuit ground node includes an NMOS isolation transistor through which the programming voltage is coupled, and a charge pump that applies a voltage having at least the magnitude of the programming voltage to the gate of the NMOS transistor. As a result, the NMOS transistor is able to pass the full magnitude of the programming voltage to the circuit ground node. The charge pump can generate a voltage having a sufficient magnitude with only a single charge pump stage because the charge pump uses the relatively large programming voltage as the starting point for the voltage boosting process.

摘要翻译： 用于将大的编程电压从外部端子耦合到电路接地节点的隔离电路包括耦合编程电压的NMOS隔离晶体管，以及将至少具有编程电压的大小的电压施加到 NMOS晶体管的栅极。 结果，NMOS晶体管能够将编程电压的全部幅度传递到电路接地节点。 由于电荷泵使用相对较大的编程电压作为升压过程的起始点，所以电荷泵可以仅使用单个电荷泵级来产生足够大的电压。

公开(公告)号：US06791352B2

公开(公告)日：2004-09-14

申请号：US10072103

申请日：2002-02-08

申请人： David Joel Verdoorn ,  Sandra S. Woodward

发明人： David Joel Verdoorn ,  Sandra S. Woodward

IPC分类号： H03K19173

CPC分类号： G01R31/31705 ,  G01R31/317 ,  G01R31/31704

摘要： In a first aspect, an apparatus is provided that is adapted to multiplex debug signals of an integrated circuit. The apparatus includes at least a first multiplexing circuit and a second multiplexing circuit. The first multiplexing circuit is adapted to receive first debug signals from the integrated circuit and to selectively multiplex at least a first portion of the first debug signals onto a first bus. The second multiplexing circuit is adapted to receive second debug signals from the integrated circuit and to selectively multiplex at least a first portion of the second debug signals onto a second bus. The apparatus further includes a logic circuit adapted to combine any debug signals of the first and second buses onto a third bus. An output stage of the apparatus is adapted to selectively output debug signals of the third bus. Numerous other aspects are provided, as are systems and methods.

摘要翻译： 在第一方面，提供一种适于复用集成电路的调试信号的装置。 该装置至少包括第一复用电路和第二复用电路。 第一复用电路适于从集成电路接收第一调试信号，并且将第一调试信号的至少第一部分选择性地复用到第一总线上。 第二复用电路适于从集成电路接收第二调试信号，并且将第二调试信号的至少第一部分选择性地复用到第二总线上。 该装置还包括适于将第一和第二总线的任何调试信号组合到第三总线上的逻辑电路。 该装置的输出级适于选择性地输出第三总线的调试信号。 还提供了许多其他方面，系统和方法也是如此。

公开(公告)号：US06768336B2

公开(公告)日：2004-07-27

申请号：US10166008

申请日：2002-06-11

申请人： Uzi Y. Vishkin ,  Joseph F. Nuzman

发明人： Uzi Y. Vishkin ,  Joseph F. Nuzman

IPC分类号： H03K19173

CPC分类号： H04L12/40013 ,  H04L12/40032

摘要： The invention relates to an interconnect, and to interconnect architecture, for communicating between processing elements and memory modules in a computer system comprising on-chip parallel computation, in order to reduce the tight synchrony that is required by important components of most present computers.

摘要翻译： 本发明涉及一种互连和互连架构，用于在包括片上并行计算的计算机系统中的处理元件和存储器模块之间进行通信，以便减少大多数当前计算机的重要部件所需的紧密同步。

公开(公告)号：US06762618B1

公开(公告)日：2004-07-13

申请号：US10269439

申请日：2002-10-11

申请人： Jinghui Zhu

发明人： Jinghui Zhu

IPC分类号： H03K19173

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17736

摘要： An efficient verify scheme for a multi-level routing structure is provided. For example, a two-level routing structure may have a second-level routing structure whose switch matrix is either partially or fully populated. Depending upon the type of fuse population, a test signal is applied either to the input side or the output side of the fuses in the second switch matrix.

摘要翻译： 提供了一种多级路由结构的有效验证方案。 例如，两级路由结构可以具有其部分或完全填充其交换矩阵的二级路由结构。 根据熔丝种类的类型，将测试信号施加到第二开关矩阵中的熔丝的输入侧或输出侧。

公开(公告)号：US06710622B1

公开(公告)日：2004-03-23

申请号：US10121179

申请日：2002-04-12

申请人： Wai Cheong Chan

发明人： Wai Cheong Chan

IPC分类号： H03K19173

CPC分类号： H03K5/06 ,  H03K3/033 ,  H03K5/05

摘要： In a one-shot, the pulse duration is adjustable through the use of a counter and one or more programmable delay lines in one or more of the feedback loops of the one-shot. The one-shot makes use of at least two flip-flops, and the output of the counter resets the flip-flops.

摘要翻译： 在单次触发中，脉冲持续时间可以通过使用计数器和一个或多个可编程延迟线来调整，该延迟线在一次性的一个或多个反馈回路中。 单触发器使用至少两个触发器，并且计数器的输出复位触发器。

公开(公告)号：US06628141B1

公开(公告)日：2003-09-30

申请号：US09711010

申请日：2000-11-13

申请人： Jürgen Alt ,  Marc-Pascal Bringmann ,  Peter Muhmenthaler

发明人： Jürgen Alt ,  Marc-Pascal Bringmann ,  Peter Muhmenthaler

IPC分类号： H03K19173

CPC分类号： G01R31/318558 ,  G01R31/318505

摘要： An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan register chain. The at least one scan register chain is configured such that data can be input into the scan register chain either via the output terminals of one of the circuit parts or via the input and/or output terminals of the integrated circuit. In addition, data can be output from the scan register chain either at the input terminals of one of the circuit parts or at the input and/or output terminals of the integrated circuit.

摘要翻译： 集成电路的特征在于，其中包含的电路部分经由包含至少一个扫描寄存器链的接口相互连接。 至少一个扫描寄存器链被配置为使得可以经由电路部件之一的输出端子或经由集成电路的输入和/或输出端子将数据输入到扫描寄存器链。 此外，数据可以从扫描寄存器链输出，或者在集成电路的一个电路部分的输入端或输入和/或输出端。

公开(公告)号：US06617874B2

公开(公告)日：2003-09-09

申请号：US10038196

申请日：2002-01-02

申请人： Lawrence S. Uzelac

发明人： Lawrence S. Uzelac

IPC分类号： H03K19173

CPC分类号： H03K3/356008 ,  H03K17/223 ,  H03K2217/0036

摘要： A power-up reference circuit and related method that generates a reference voltage in response to the circuit being powered up. The circuit includes a power-up sensing circuit that generates a set signal, a latch to generate and sustain the reference voltage in response to the set signal, and a reset key decoder to receive an N-bit key and in response thereto generate a reset signal that causes the latch to reset. Upon the circuit being powered up, the power-up sensing circuit generates the set signal which sets the latch to generate the reference voltage. The reference voltage can be used by other circuits to initialize their operating conditions. Once the reference voltage has been used, the N-bit key is generated which causes the decoder to generate the reset signal, which in turn, causes the latch to reset. When the latch is reset, the power-up reference circuit consumes substantially no power.

摘要翻译： 上电参考电路和相关方法，其响应于电路被加电产生参考电压。 该电路包括产生设置信号的上电感测电路，响应于设定信号产生和维持参考电压的锁存器，以及用于接收N位密钥的复位密钥解码器，并且响应于此产生复位 信号使锁存器复位。 在电路通电时，上电感测电路产生设置锁存器以产生参考电压的置位信号。 其他电路可以使用参考电压来初始化其工作条件。 一旦使用了参考电压，就产生N位键，使得解码器产生复位信号，这又导致锁存器复位。 当锁存器复位时，上电参考电路基本上不消耗电能。

公开(公告)号：US06580288B1

公开(公告)日：2003-06-17

申请号：US09392837

申请日：1999-09-09

申请人： Kenneth Douglas Klapproth

发明人： Kenneth Douglas Klapproth

IPC分类号： H03K19173

CPC分类号： H03K19/1732 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

摘要： The present invention is embodied in a system and method for sharing input and output pins between a plurality of separate logic circuits coexisting within a single microprocessor such that the microprocessor is capable of assuming the characteristics of a desired logic circuit. The present invention achieves controlled sharing of bidirectional input and output pins without the requirement to use multiplexing logic. Because the pins may be shared among a plurality of logic circuits, a single microchip may be used for completely different purposes by enabling or disabling selected logic circuits. In other words, a single microchip can take on any number of properties by simply enabling one or more logic circuits while disabling other.

摘要翻译： 本发明体现在用于在单个微处理器内共存的多个分离的逻辑电路之间共享输入和输出引脚的系统和方法，使得微处理器能够承担所需逻辑电路的特性。 本发明实现双向输入和输出引脚的可控共享，而不需要使用复用逻辑。 因为引脚可以在多个逻辑电路之间共享，所以通过启用或禁用所选择的逻辑电路，可以将单个微芯片用于完全不同的目的。 换句话说，单个微芯片可以通过简单地启用一个或多个逻辑电路同时禁用另一个来承担任何数量的属性。

公开(公告)号：US06529040B1

公开(公告)日：2003-03-04

申请号：US09566052

申请日：2000-05-05

申请人： Richard A. Carberry ,  Steven P. Young ,  Trevor J. Bauer

发明人： Richard A. Carberry ,  Steven P. Young ,  Trevor J. Bauer

IPC分类号： H03K19173

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The read decoder includes a multiplexing circuit made up of a series of multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD. In one embodiment, a configurable logic block is provided with a single write decoder that is shared by a first LUT and a second LUT.

摘要翻译： 用于可编程逻辑器件（PLD）的快速，节省空间的查找表（LUT），其中修改LUT的写解码器，读取解码器和存储器块以提供高性能，同时提供高效布局。 写解码器和读取解码器都由LUT输入信号控制，数据信号被直接发送到存储器块的每个存储电路（即不经过写入解码器）。 读取解码器包括由一系列多路复用器组成的复用电路，该多路复用器由从PLD的互连资源接收的输入信号直接控制。 在一个实施例中，可配置逻辑块被提供有由第一LUT和第二LUT共享的单个写入解码器。

公开(公告)号：US06529038B2

公开(公告)日：2003-03-04

申请号：US09736898

申请日：2000-12-13

申请人： Roy T. Lambertson

发明人： Roy T. Lambertson

IPC分类号： H03K19173

CPC分类号： G11C17/18

摘要： A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more positive potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse. The disruption of the antifuse material is sensed and the programming pulse is extended for a fixed period of time following the disruption of the antifuse material. The programming pulse is followed by a soak pulse having a polarity having a polarity such that a more negative potential is applied to the upper electrode of the antifuse than to the lower electrode of the antifuse.