发明授权
US06310815B1 Multi-bank semiconductor memory device suitable for integration with logic
失效
适合与逻辑集成的多存储半导体存储器件
- 专利标题： Multi-bank semiconductor memory device suitable for integration with logic
- 专利标题（中）： 适合与逻辑集成的多存储半导体存储器件
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申请号： US09131346申请日： 1998-08-07
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公开(公告)号： US06310815B1公开(公告)日： 2001-10-30
- 发明人: Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
- 申请人： Tadato Yamagata , Akira Yamazaki , Shigeki Tomishima , Yoshio Yukinari , Makoto Hatakenaka , Atsushi Miyanishi
- 优先权： JP9-300734 19971031; JP10-095778 19980408
- 主分类号： G11C800
- IPC分类号： G11C800
摘要：
Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.
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