Flow of data units to an address resolution processor is controlled to inhibit multiple data units from a single multicast flow from being enqueued with the address resolution processor. In a switch having a plurality of Input/Output Application Specific Integrated Circuits (“I/O ASICs”) with a plurality of ports, no more than one data unit from each I/O ASIC is permitted to be enqueued with the address resolution processor at any point in time. A separate learn pending indicator may be defined for each I/O ASIC in the switch.