发明授权
- 专利标题: Pseudo-static leakage-tolerant register file bit-cell circuit
- 专利标题(中): 伪静态容错寄存器文件位单元电路
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申请号: US09733225申请日: 2000-12-08
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公开(公告)号: US06320795B1公开(公告)日: 2001-11-20
- 发明人: Ganesh Balamurugan , Ram K. Krishnamurthy
- 申请人: Ganesh Balamurugan , Ram K. Krishnamurthy
- 主分类号: G11C700
- IPC分类号: G11C700
摘要:
A register file for use within, for example, a microprocessor or other digital processing device includes a register file cell having a pull down transistor that is driven by a static logic circuit (e.g., a NOR gate). During a read operation, the static logic circuit causes the pull down transistor to discharge a dynamic bit line node when a predetermined data value is stored within a data storage area of the register file cell. The logic circuit serves to isolate the input terminal of the pull down transistor from a potentially noisy read signal received by the register file cell, thus preventing noise induced leakage currents from being created. In one embodiment, a bias circuit is provided that applies a bias signal to the pull down transistor during non-read intervals to significantly reduce leakage currents flowing through the pull down transistor at these times.
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