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30 条记录 (耗时 0.013 秒)

    Link calibration
    3.
    发明授权
    Link calibration 有权
    链接校准

    公开(公告)号：US08064536B2

    公开(公告)日：2011-11-22

    申请号：US11964598

    申请日：2007-12-26

    申请人： Ganesh Balamurugan ,  Joseph Kennedy

    发明人： Ganesh Balamurugan ,  Joseph Kennedy

    IPC分类号： H04L27/00

    CPC分类号： H04L25/03878 ,  H04L1/0002 ,  H04L25/0272 ,  H04L25/0282 ,  H04L25/0292

    摘要： In some embodiments, provided are methods and circuits to control the power efficiency of a transceiver or a transmitter in a scalable I/O link (a link whose bandwidth and power can be adjusted to meet changing performance demands).

    摘要翻译： 在一些实施例中，提供了用于控制可伸缩I / O链路（能够调整其带宽和功率以满足不断变化的性能需求的链路）的收发器或发射机的功率效率的方法和电路。

    System and apparatus of reconfigurable transceiver design for multi-mode signaling
    4.
    发明授权
    System and apparatus of reconfigurable transceiver design for multi-mode signaling 有权
    用于多模式信令的可重配置收发器设计的系统和装置

    公开(公告)号：US07919984B2

    公开(公告)日：2011-04-05

    申请号：US12347858

    申请日：2008-12-31

    申请人： Ganesh Balamurugan ,  Bryan Casper

    发明人： Ganesh Balamurugan ,  Bryan Casper

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018585

    摘要： A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

    摘要翻译： 对于广泛的I / O系统要求可重新配置的收发器。 可重配置收发器的可重构发射机能够通过电流和电压模式信令在单端和差模中传输多电平信号。 可以对所有发送模式预先强调要传输的信号。 可重新配置的收发器可以根据性能指标动态调整带宽和功耗。

    Adaptive equalization using a conditional update sign-sign least mean square algorithm
    5.
    发明授权
    Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
    使用条件更新符号最小均方算法进行自适应均衡

    公开(公告)号：US07289557B2

    公开(公告)日：2007-10-30

    申请号：US10660228

    申请日：2003-09-10

    申请人： Ganesh Balamurugan ,  Bryan K. Casper ,  James E. Jaussi ,  Stephen R. Mooney

    发明人： Ganesh Balamurugan ,  Bryan K. Casper ,  James E. Jaussi ,  Stephen R. Mooney

    IPC分类号： H03D3/22 ,  H04L27/22

    CPC分类号： H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

    摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：<？in-line-formula description =“In-line 公式“end =”lead“？> h（t + 1）= h（t）+ mu [sgn {d（t）} - t）-Kd（t）}] sgn { x（t）}，<？in-line-formula description =“In-line Formulas”end =“tail”？> OSTYLE =“SINGLE”> h（t）是表示FIR滤波器的滤波器抽头的滤波器向量，x（t）是表示接收数据的当前和过去采样的数据x（t） t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，mu决定适配的存储器或窗口大小，K是考虑到实际限制的比例因子 通信信道，接收机和均衡器。 此外，提供了用于校准比例因子K的过程和电路结构。

    Pseudo-static leakage-tolerant register file bit-cell circuit
    6.
    发明授权
    Pseudo-static leakage-tolerant register file bit-cell circuit 有权
    伪静态容错寄存器文件位单元电路

    公开(公告)号：US06320795B1

    公开(公告)日：2001-11-20

    申请号：US09733225

    申请日：2000-12-08

    申请人： Ganesh Balamurugan ,  Ram K. Krishnamurthy

    发明人： Ganesh Balamurugan ,  Ram K. Krishnamurthy

    IPC分类号： G11C700

    CPC分类号： G11C7/106 ,  G11C7/1051

    摘要： A register file for use within, for example, a microprocessor or other digital processing device includes a register file cell having a pull down transistor that is driven by a static logic circuit (e.g., a NOR gate). During a read operation, the static logic circuit causes the pull down transistor to discharge a dynamic bit line node when a predetermined data value is stored within a data storage area of the register file cell. The logic circuit serves to isolate the input terminal of the pull down transistor from a potentially noisy read signal received by the register file cell, thus preventing noise induced leakage currents from being created. In one embodiment, a bias circuit is provided that applies a bias signal to the pull down transistor during non-read intervals to significantly reduce leakage currents flowing through the pull down transistor at these times.

    摘要翻译： 在例如微处理器或其它数字处理装置中使用的寄存器文件包括具有由静态逻辑电路（例如，或非门）驱动的下拉晶体管的寄存器文件单元。 在读取操作期间，当预定数据值存储在寄存器文件单元的数据存储区域内时，静态逻辑电路使下拉晶体管放电动态位线节点。 逻辑电路用于将下拉晶体管的输入端与由寄存器堆单元接收的潜在噪声读信号隔离，从而防止产生噪声感应的漏电流。 在一个实施例中，提供偏置电路，其在非读取间隔期间向下拉晶体管施加偏置信号，以显着减少在这些时间流过下拉晶体管的漏电流。

    Method and apparatus to perform on-die waveform capture
    9.
    发明申请
    Method and apparatus to perform on-die waveform capture 有权
    执行管芯上波形捕获的方法和装置

    公开(公告)号：US20050134369A1

    公开(公告)日：2005-06-23

    申请号：US10743349

    申请日：2003-12-23

    申请人： Bryan Casper ,  Aaron Martin ,  James Jaussi ,  Stephen Mooney ,  Ganesh Balamurugan

    发明人： Bryan Casper ,  Aaron Martin ,  James Jaussi ,  Stephen Mooney ,  Ganesh Balamurugan

    IPC分类号： H03F1/02

    CPC分类号： H03K5/19

    摘要： An integrated circuit is provided that includes a first port to receive a first signal from a first channel and a first device coupled to the first port to modify a channel response of the first signal received from the first channel. A waveform capture device may be coupled to the first device to capture a waveform of a signal modified by the first device.

    摘要翻译： 提供一种集成电路，其包括从第一信道接收第一信号的第一端口和耦合到第一端口的第一设备，以修改从第一信道接收的第一信号的信道响应。 波形捕获装置可以耦合到第一装置以捕获由第一装置修改的信号的波形。

    Adaptive equalization using a conditional update sign-sign least mean square algorithm
    10.
    发明申请
    Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
    使用条件更新符号最小均方算法进行自适应均衡

    公开(公告)号：US20050053125A1

    公开(公告)日：2005-03-10

    申请号：US10660228

    申请日：2003-09-10

    申请人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

    发明人： Ganesh Balamurugan ,  Bryan Casper ,  James Jaussi ,  Stephen Mooney

    IPC分类号： H03H21/00 ,  H04L25/03 ,  H03K5/159

    CPC分类号： H03H21/0043 ,  H03H21/0001 ,  H03H2021/0065 ,  H04L25/03038 ,  H04L25/03885 ,  H04L2025/03477 ,  H04L2025/03617

    摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: {overscore (h)}(t+1)={overscore (h)}(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{{overscore (x)}(t)}, where {overscore (h)}(t) is the filter vector representing the filter taps of the FIR filter, {overscore (x)}(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.

    摘要翻译： 用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中在训练序列期间通过执行更新的电路迭代地更新滤波器：{overscore（h（t + 1）= {overscore（ h（t）+ mu [sgn {d（t）} - sgn {z（t）-Kd（t）}] sgn {{overscore（x（t）}，其中{overscore（h（t） 表示FIR滤波器的滤波器抽头的向量{overscore（x（t））是表示接收数据x（t）的当前和过去样本的数据向量，d（t）是用于训练的期望数据，z ）是FIR滤波器的输出，mu确定适配的存储器或窗口大小，K是考虑到通信信道，接收机和均衡器的实际限制的比例因子，并且提供了一个过程和电路结构 用于校准比例因子K.