发明授权
US06321185B1 Estimation system of LSI power consumption 失效
LSI功耗估算系统

  • 专利标题: Estimation system of LSI power consumption
  • 专利标题(中): LSI功耗估算系统
  • 申请号: US09252891
    申请日: 1999-02-19
  • 公开(公告)号: US06321185B1
    公开(公告)日: 2001-11-20
  • 发明人: Naoya Takahashi
  • 申请人: Naoya Takahashi
  • 优先权: JP10-047722 19980227
  • 主分类号: G06F1750
  • IPC分类号: G06F1750
Estimation system of LSI power consumption
摘要:
Power consumption of an LSI chip is estimated at the beginning stage of the designing without using the HDL description. An I/O part power of a new designing LSI chip is calculated by an equation with using the outside specifications required by the application of the LSI chip. An I/O part power of an original LSI chip is calculated by the outside specifications, the core circuitry part power of the original LSI chip is calculated by subtracting this calculated I/O part power of the original LSI chip from the known total power of the original LSI chip, and converting the voltage and process and frequency, the core circuitry part power of the new designing LSI chip is calculated. The kinds of functions, voltage, frequency, the number of gates, unit capacity and clock structure of the new designing LSI chip are given and referring to the data base of ratio of each function described the ratio of the number of FF and the ratio of clock power/logic power, the clock system power is calculated by the number of FF and the clock structure. The logic system power is calculated by the ratio of the clock power/the logic power. The modifiable circuitry part power is calculated by summing up the I/O part power, the core circuitry part power, the clock system power and the logic system power.
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