发明授权
- 专利标题: Method for fabricating transistors
- 专利标题(中): 晶体管制造方法
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申请号: US09175267申请日: 1998-10-20
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公开(公告)号: US06323103B1公开(公告)日: 2001-11-27
- 发明人: Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
- 申请人: Rajesh Rengarajan , Jochen Beintner , Ulrike Gruening , Hans-Oliver Joachim
- 主分类号: H01L218238
- IPC分类号: H01L218238
摘要:
A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.