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公开(公告)号：US07102908B2
公开(公告)日：2006-09-05
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译： 本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。 铁电测量电容器电连接在铁电存储电容器和读出放大器之间。
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公开(公告)号：US06903959B2
公开(公告)日：2005-06-07
申请号：US10065168
申请日：2002-09-24
摘要： A memory IC having improved sensing during reads is disclosed. The IC includes the use of first and second reference voltages for sensing to compensate for asymmetry that exists between cells on bitline true and bitline complement. The first reference voltage is used for sensing a cell on bitline true while the second reference voltage is used for sensing a cell on bitline complement.
摘要翻译： 公开了一种在读取期间具有改进的感测的存储器IC。 IC包括使用第一和第二参考电压进行感测以补偿存在于位线真数和位线补码之间的单元之间的不对称性。 第一个参考电压用于在位线真时感测单元，而第二个参考电压用于感测位线补码上的单元。
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3.发明授权2T2C signal margin test mode using a defined charge exchange between BL and/BL 失效2T2C信号余量测试模式，使用BL和/ BL之间定义的电荷交换公开(公告)号：US06876590B2
公开(公告)日：2005-04-05
申请号：US10301548
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
发明人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。 半导体存储器测试模式配置包括用于存储数字数据并通过第一选择晶体管将单元板线连接到第一位线的第一电容器。 通过连接到字线而激活的第一选择晶体管。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 第三晶体管在第一和第二位线之间传输电荷，以减少差分读取信号。
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公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译： 数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。 最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。 这可以非常快速地完成，因为FeRAM器件具有高写入速率。 随后，控制器将数据传送到闪存单元。 因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。
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公开(公告)号：US06323103B1
公开(公告)日：2001-11-27
申请号：US09175267
申请日：1998-10-20
IPC分类号： H01L218238
CPC分类号： H01L21/823878 , H01L21/762
摘要： A method is provided for fabricating a first and second MOSFET transistors in different electrically isolated active areas of a semiconductor body, each one of the transistors having a plurality of layers. A first gate oxide layer and a first poly-crystalline silicon layer are deposited over the semiconductor body over the active areas. Trenches are etched in said first gate oxide and poly-crystalline silicon layers and said semiconductor body to delineate the first and second active areas, thereby forming first delineated gate oxide layer and poly-crystalline silicon layers coextensive with the first active area. Material is deposited in said trenches to form the active area isolations, the active area isolations having a top surface above said semiconductor body. A masking layer is then formed over said first and second active areas and selective portions of it are removed to expose said second active area. The masking layer and the active area isolations together form a mask defining an opening coextensive with the second active area with the active area isolations defining said opening. Material through the opening to form a second gate oxide layer and a second poly-crystalline layer, such second layer and second poly-crystalline layer being coextensive with the second active area. The first transistor with the first delineated gate oxide and poly-crystalline layer as a pair of the plurality of layers of the first transistor and the second transistor with the second gate oxide layer and second poly-crystalline layer as a pair of the plurality of layers of the second transistor.
摘要翻译： 提供了一种用于在半导体主体的不同电隔离有源区中制造第一和第二MOSFET晶体管的方法，每个晶体管具有多个层。 第一栅极氧化物层和第一多晶硅层沉积在半导体主体上方的有源区域上。 在所述第一栅极氧化物和多晶硅层和所述半导体本体中蚀刻沟槽以描绘第一和第二有源区，从而形成与第一有源区共同延伸的第一划定的栅极氧化物层和多晶硅层。 材料沉积在所述沟槽中以形成有源区隔离，所述有源区隔离在所述半导体本体上方具有顶表面。 然后在所述第一和第二有源区上形成掩模层，并且去除其选择性部分以暴露所述第二有源区。 屏蔽层和有源区隔离一起形成掩模，其限定与第二有源区域共同延伸的开口，其中限定所述开口的有源区隔离。 通过开口的材料形成第二栅氧化层和第二多晶层，这种第二层和第二多晶层与第二有源区共同延伸。 第一晶体管，其具有第一划定的栅极氧化物和多晶层作为第一晶体管的多个层和第二晶体管的一对，其中第二栅极氧化物层和第二多晶层作为一对多个层 的第二晶体管。
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公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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公开(公告)号：US06906969B2
公开(公告)日：2005-06-14
申请号：US10065169
申请日：2002-09-24
CPC分类号： G11C29/785 , G11C17/14
摘要： A redundancy unit includes first and second fuse blocks for programming the redundancy element. One fuse block has laser blowable fuses and the other electrical fuses. The redundancy unit can be programmed by either one of the fuse blocks, enabling the redundancy unit to able to be used for defects identified before packaging and as well as after.
摘要翻译： 冗余单元包括用于对冗余元件进行编程的第一和第二熔丝块。 一个保险丝盒有激光熔断保险丝和其他电气保险丝。 冗余单元可以由任一个保险丝块编程，使得冗余单元能够用于在封装之前以及之后识别的缺陷。
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公开(公告)号：US06856560B2
公开(公告)日：2005-02-15
申请号：US10133764
申请日：2002-04-26
CPC分类号： G11C29/816 , G11C11/22
摘要： An improved redundancy scheme for chained memory architecture is disclosed. The redundancy scheme comprises including redundant cells as part of the memory chain. As such, a redundant cell is used to repair a defective cell within the chain. This eliminates the need in conventional chained architecture to replace the whole memory block when there is a defective cell.
摘要翻译： 公开了用于链接存储器架构的改进的冗余方案。 冗余方案包括作为存储器链的一部分的冗余单元。 因此，使用冗余单元来修复链中的有缺陷的单元。 这消除了在传统链式结构中当存在缺陷单元时替换整个存储器块的需要。
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9.发明授权2T2C signal margin test mode using a defined charge and discharge of BL and /BL 失效2T2C信号余量测试模式使用BL和/ BL定义充放电公开(公告)号：US06826099B2
公开(公告)日：2004-11-30
申请号：US10301529
申请日：2002-11-20
IPC分类号： G11C700
摘要： A semiconductor memory test mode configuration includes a first capacitor for storing digital data. The first capacitor connects a cell plate line to a first bit line through a first select transistor which is activated through a connection to a word line. A second capacitor for storing digital data connects the cell plate line to a second bit line through a second select transistor which is also activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines for measuring a differential read signal on the first and second bit lines. A constant current mover, for example a constant current sink or source, is connected to the first bit line through a third transistor for changing the amount of charge on the first bit line when the third transistor is turned on to reduce the differential read signal.
摘要翻译： 半导体存储器测试模式配置包括用于存储数字数据的第一电容器。 第一电容器通过第一选择晶体管将单元板线连接到第一位线，该第一选择晶体管通过与字线的连接被激活。 用于存储数字数据的第二电容器通过第二选择晶体管将单元板线连接到第二位线，第二选择晶体管也通过与字线的连接而被激活。 感测放大器连接到第一和第二位线，用于测量第一和第二位线上的差分读取信号。 恒定电流移动器，例如恒定电流吸收器或源极，通过第三晶体管连接到第一位线，用于当第三晶体管导通时改变第一位线上的电荷量，以减小差分读取信号。
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10.发明授权Deep divot mask for enhanced buried-channel PFET performance and reliability 失效深埋式掩模，增强了埋地通道PFET性能和可靠性公开(公告)号：US06323532B1
公开(公告)日：2001-11-27
申请号：US09609379
申请日：2000-07-03
IPC分类号： H01L2900
CPC分类号： H01L27/0928 , H01L21/76237
摘要： A semiconductor structure comprises first gate conductors which wrap around N-wells of buried-channel P-type metal oxide semiconductor field effect transistors and second gate conductors which do not wrap around P-wells of surface-channel N-type metal oxide semiconductor field effect transistors and a method of manufacturing the same comprises forming insulators adjacent each of the N-wells and the P-wells, protecting the N-wells with a patterned mask, forming first divots in areas of the insulators adjacent the N-wells and forming second divots in areas of the insulators P-wells, wherein the first divots have a greater depth than the second divots.
摘要翻译： 半导体结构包括第一栅极导体，其围绕掩埋沟道P型金属氧化物半导体场效应晶体管的N阱和不包围表面沟道N型金属氧化物半导体场效应的P阱的第二栅极导体 晶体管及其制造方法包括在每个N阱和P阱附近形成绝缘体，用图案化掩模保护N阱，在与N阱相邻的绝缘体的区域中形成第一个纹理并形成第二个 在绝缘子P井的区域中的凹坑，其中第一个纹理具有比第二个纹理更大的深度。
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