发明授权
- 专利标题: Method for manufacturing a semiconductor device
- 专利标题(中): 半导体器件的制造方法
-
申请号: US09361989申请日: 1999-07-28
-
公开(公告)号: US06326299B1公开(公告)日: 2001-12-04
- 发明人: Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
- 申请人: Yoshio Homma , Seiichi Kondo , Noriyuki Sakuma , Naofumi Ohashi , Toshinori Imai , Hizuru Yamaguchi , Nobuo Owada
- 优先权: JP10-317233 19981109
- 主分类号: H01L214763
- IPC分类号: H01L214763
摘要:
In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.
信息查询