Invention Grant
US06327176B1 Single event upset (SEU) hardened latch circuit 有权
单事件镦粗(SEU)硬化锁存电路

  • Patent Title: Single event upset (SEU) hardened latch circuit
  • Patent Title (中): 单事件镦粗(SEU)硬化锁存电路
  • Application No.: US09844079
    Application Date: 2001-04-26
  • Publication No.: US06327176B1
    Publication Date: 2001-12-04
  • Inventor: Bin LiDavid C. Lawson
  • Applicant: Bin LiDavid C. Lawson
  • Main IPC: G11C11412
  • IPC: G11C11412
Single event upset (SEU) hardened latch circuit
Abstract:
A single event upset hardened latch circuit is disclosed. The single event hardened latch circuit includes a first dual-port inverter and a second dual-port inverter. An input is coupled to the first dual-port inverter via a first set of pass gates. The first dual-port inverter is coupled to the second dual-port inverter via a second set of pass gates. The output is connected to the first and second dual-port inverters.
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