发明授权
- 专利标题: Wafer burn-in design for DRAM and FeRAM devices
- 专利标题(中): DRAM和FeRAM器件的晶片老化设计
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申请号: US09274001申请日: 1999-03-22
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公开(公告)号: US06327682B1公开(公告)日: 2001-12-04
- 发明人: Pien Chien , Jin-Yuan Lee
- 申请人: Pien Chien , Jin-Yuan Lee
- 主分类号: G11C2900
- IPC分类号: G11C2900
摘要:
In this invention is disclosed a method of burn-in testing either DRAM's or FeRAM's at the wafer level. A stress voltage is applied across all storage capacitors of a DRAM or a FeRAM during a wafer level burn-in test to weed out memory chips with weak memory cells. Three pads are added to the memory chips to accommodate a burn-in signal, a word line voltage and a stress voltage. The burn-in signal disables normal memory operations, powers on all word lines, and connects a stress voltage across the storage capacitors of the memory cells. The stress voltage across the storage capacitors is the difference between the externally applied stress voltage and a low voltage from the bit lines that is connected to the memory cells by means of the word lines. The wafer level burn-in provides a way to improve throughput by eliminating weak product early in the manufacturing process.
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