公开(公告)号：US06434033B1

公开(公告)日：2002-08-13

申请号：US09726473

申请日：2000-11-30

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1500

CPC分类号： G11C29/70 ,  G11C11/408 ,  G11C15/00 ,  G11C29/789 ,  G11C29/846

摘要： A DRAM module and a method of replacing a damaged DRAM cell in the DRAM module with a SRAM. The DRAM module has at least a non-volatile memory and a DRAM control logic circuit. In the process of replacing the damaged DRAM with the SRAM, the damaged address data is compared to DRAM address data. If the data are consistent, the address of the SRAM is used to access data. Meanwhile, the output enabling signal of the DRAM cell is turned off. It can thus assist the computer to correctly find the good DRAM cell for data access, so as to ensure a normal operation of the computer.

摘要翻译： DRAM模块和用SRAM替代DRAM模块中损坏的DRAM单元的方法。 DRAM模块至少具有非易失性存储器和DRAM控制逻辑电路。 在用SRAM替换损坏的DRAM的过程中，将损坏的地址数据与DRAM地址数据进行比较。 如果数据一致，则使用SRAM的地址来访问数据。 同时，关闭DRAM单元的输出使能信号。 因此，它可以帮助计算机正确找到用于数据访问的良好DRAM单元，以确保计算机的正常运行。

公开(公告)号：US06405331B1

公开(公告)日：2002-06-11

申请号：US09359448

申请日：1999-07-22

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C2900

CPC分类号： G11C29/12 ,  G11C29/48 ,  G11C2207/104

摘要： A method is provided for performing a BIST (built-in self test) procedure on embedded memory through a time-division multipexed scheme with a reduced number of probing pads. This method is characterized in the use of a time-division multipexed scheme to obtain the addresses of bad memory cells so that these address data can be used to indicate the locations of the bad memory cells during repair process. Moreover, this method is characterized in that it requires only a fewer number of probing pads than the prior art so that the required layout area for the BIST procedure can be reduced as compared to the prior art. This method is therefore more cost-effective to implement than the prior art.

摘要翻译： 提供了一种通过具有减少的探测焊盘数量的时分多重方案对嵌入式存储器执行BIST（内置自检）程序的方法。 该方法的特征在于使用时分多路复用方案来获得不良存储器单元的地址，使得这些地址数据可用于指示在修复过程中坏存储器单元的位置。 此外，该方法的特征在于，其仅需要比现有技术少的探测焊盘数量，因此与现有技术相比可以减少BIST过程所需的布局面积。 因此，该方法比现有技术更具成本效益。

公开(公告)号：US06366514B1

公开(公告)日：2002-04-02

申请号：US09620032

申请日：2000-07-20

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G06F1216

CPC分类号： G11C11/406

摘要： The present invention provides a memory refresh structure having a memory array and two clock generators. The memory array has a plurality of cells grouped into original segments. The two clock generators generate two clock signals, CLK0 and CLK1. CLK0 takes responsibility for the refresh operations of the cells in the original segments to meet an original refresh time. A portion of the original segments that having at least one cell whose retention time is longer than the original refresh time are defined as first segments. CLK1 takes responsibility for the refresh operations of the cells in the first segments to make the refreshed cell meet a first refresh time shorter than the original refresh time.

摘要翻译： 本发明提供一种具有存储器阵列和两个时钟发生器的存储器刷新结构。 存储器阵列具有分组成原始段的多个单元。 两个时钟发生器产生两个时钟信号CLK0和CLK1。 CLK0负责原始片段中的单元格的刷新操作，以满足原始刷新时间。 具有保留时间长于原始刷新时间的至少一个单元的原始段的一部分被定义为第一段。 CLK1负责第一段中的单元的刷新操作，使刷新的单元满足比原始刷新时间短的第一刷新时间。

公开(公告)号：US5946248A

公开(公告)日：1999-08-31

申请号：US32401

申请日：1998-02-27

申请人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

发明人： Pien Chien ,  Shih-Chin Lin ,  Charlie Han

IPC分类号： G01R31/28 ,  G11C29/50 ,  G11C13/00

CPC分类号： G11C29/50 ,  G01R31/2856 ,  G11C11/401

摘要： A method is provided for use on a wafer formed with a plurality of dice on each of which a memory device, such as a DRAM (dynamic random access memory) device to perform a burn-in operation on the memory device so as to test the reliability thereof. By this method, a plurality of pads are formed in the scribe lines that are used as reference marks in the cutting apart of the dice. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the dice where each memory device is formed. The burn-in operation is more convenient, quick, and cost-effective to implement.

摘要翻译： 提供一种在形成有多个骰子的晶片上使用的方法，每个骰子上具有诸如DRAM（动态随机存取存储器）设备的存储器件，以在存储器件上执行老化操作，以便测试 可靠性。 通过这种方法，在切割线中用作参考标记的划线中形成多个焊盘。 这些焊盘用于将外部产生的老化使能信号和直流偏置电压传送到每个存储器件。 由于用于老化线的焊盘形成在划线中，所以它们在形成每个存储器件的骰子上不会占用额外的空间。 老化操作更加方便，快捷，性价比高。

公开(公告)号：US06760249B2

公开(公告)日：2004-07-06

申请号：US10176238

申请日：2002-06-19

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1100

CPC分类号： G11C11/406 ,  G11C8/16 ,  G11C15/04 ,  G11C15/043

摘要： A NAND or NOR content-addressable memory (CAM) cell, which selectively use single port, tow ports, or three ports for operations depending on design requirements. Only n-channel transistors or p-channel transistors design these NAND or NOR CAM cells. In such designs, one-port bit line with one-port word line, or one-port bit line with two-port word lines, or two-port bit lines with two-port word lines are provided for meeting different operations and pruposes.

摘要翻译： NAND或NOR内容可寻址存储器（CAM）单元，其选择性地使用单端口，串口或三个端口用于根据设计要求进行操作。 只有n沟道晶体管或p沟道晶体管设计这些NAND或NOR CAM单元。 在这样的设计中，提供具有单端口字线的单端口位线或具有双端口字线的单端口位线或具有双端口字线的双端口位线，以满足不同的操作和pruposes。

公开(公告)号：US06556498B2

公开(公告)日：2003-04-29

申请号：US10047765

申请日：2002-01-14

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C700

CPC分类号： G11C15/04 ,  G11C11/406 ,  G11C15/043

摘要： An operation method for a static random access memory (SRAM) device. The SRAM device has a plurality of memory cells. Each of the memory cells is periodically refreshed to retain valid data. The operation method comprising receiving an access address and a refresh address for the SRAM device and detecting whether a transition pulse and a refresh pulse being generated. The access address is used for accessing data stored in the SRAM device and the refresh address is used for periodically refreshing the memory cell in the SRAM. The transition pulse is generated by an address transition detector when a read/write operation is issued. The refresh pulse is generated in response to a refresh clock being in an active state.

公开(公告)号：US06414898B1

公开(公告)日：2002-07-02

申请号：US09759907

申请日：2001-01-16

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C800

CPC分类号： G11C11/4087 ,  G11C7/1048 ,  G11C8/10 ,  G11C8/18 ,  G11C11/4096

摘要： A decode circuit provides timing and control signals to a DRAM to insure a minimum current surge during activation of bit-lines within the DRAM during a row address strobe (RAS) cycle. Providing the minimum current surge during the RAS cycle prevents damage to a battery attached to a DRAM when the bit-lines of the DRAM are activated, while minimizing the time to access digital data retain within the DRAM array. The decode circuit within a DRAM will receive a digital address word indicating column locations of a plurality of desired digital data bits retained within an array of DRAM memory cells, decode digital address word, and selectively activate bit-lines of said column locations of said plurality of desired digital data bits at a first time and activate all remaining bit-lines at times subsequent to the first time to minimize RAS cycle current. The decode circuit has a decode logic circuit to select one of the column locations that is designated by the digital address date word. The decode circuit additionally has a first timing circuit and at least one second timing circuit. The first timing circuit is connected between the decode logic circuit and the column locations of said array of DRAM cells to activate the selected one column location to be activated at the first time. At least one second timing circuit is connected between the logic circuit and the column locations of said DRAM cells to activate all unselected locations at times subsequent to the first time.

摘要翻译： 解码电路向DRAM提供定时和控制信号，以在行地址选通（RAS）周期期间在DRAM内的位线激活期间确保最小电流浪涌。 在RAS周期期间提供最小电流浪涌可防止当DRAM的位线被激活时对连接到DRAM的电池造成损坏，同时使访问数字数据的时间最小化保留在DRAM阵列内。 DRAM内的解码电路将接收指示保留在DRAM存储单元的阵列内的多个所需数字数据位的列位置的数字地址字，解码数字地址字，并选择性地激活所述多个存储单元的列位置的位线 的所需数字数据位，并且在第一次之后的时间激活所有剩余的位线，以使RAS周期电流最小化。 解码电路具有解码逻辑电路，用于选择由数字地址日期字指定的列位置之一。 解码电路还具有第一定时电路和至少一个第二定时电路。 第一定时电路连接在解码逻辑电路和所述DRAM单元阵列的列位置之间，以激活所选择的一个列位置以在第一时间被激活。 在逻辑电路和所述DRAM单元的列位置之间连接至少一个第二定时电路，以在第一次之后的时间激活所有未选择的位置。

公开(公告)号：US20060155560A1

公开(公告)日：2006-07-13

申请号：US11033726

申请日：2005-01-13

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G06Q99/00 ,  G07G1/00 ,  G06F17/30

CPC分类号： G06Q10/0637 ,  G06Q10/06

摘要： A semiconductor market development and resource management method compriseing collecting at least one client's data regarding a semiconductor industry. The data is collected and a client management database is established. The collected data in the client management database cooperates with at least one assessment condition to analyze and convert the data into knowledge capable of supporting the enterprise management.

摘要翻译： 半导体市场开发和资源管理方法包括收集关于半导体工业的至少一个客户的数据。 收集数据并建立客户管理数据库。 客户管理数据库中收集的数据与至少一个评估条件配合，将数据分析并转换成支持企业管理的知识。

公开(公告)号：US06510069B2

公开(公告)日：2003-01-21

申请号：US09895555

申请日：2001-06-28

申请人： Pien Chien

发明人： Pien Chien

IPC分类号： G11C1500

CPC分类号： G11C15/04

摘要： An apparatus and an operation method of a content addressable memory (CAM). The content addressable memory has a memory array and a frequency multiplier. The memory array has a memory cell row, which has a plurality of memory portions and a tag-compare portion. Each memory portion is used to store bit data. The tag-compare portion receives a compare data signal, which is compared to the bit data stored in all the memory portions. The memory portions are connected to the tag-compare portion in parallel. The frequency multiplier receives an external drive signal, and outputs an internal compare signal after multiplying a frequency of the drive signal with a certain numeric. The tag-compare portion sequentially compares the compare data signal with the bit data stored in each memory portion according to the clock of the internal compare signal, and outputs a match signal.

公开(公告)号：US06327682B1

公开(公告)日：2001-12-04

申请号：US09274001

申请日：1999-03-22

申请人： Pien Chien ,  Jin-Yuan Lee

发明人： Pien Chien ,  Jin-Yuan Lee

IPC分类号： G11C2900

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C11/401 ,  G11C29/006

摘要： In this invention is disclosed a method of burn-in testing either DRAM's or FeRAM's at the wafer level. A stress voltage is applied across all storage capacitors of a DRAM or a FeRAM during a wafer level burn-in test to weed out memory chips with weak memory cells. Three pads are added to the memory chips to accommodate a burn-in signal, a word line voltage and a stress voltage. The burn-in signal disables normal memory operations, powers on all word lines, and connects a stress voltage across the storage capacitors of the memory cells. The stress voltage across the storage capacitors is the difference between the externally applied stress voltage and a low voltage from the bit lines that is connected to the memory cells by means of the word lines. The wafer level burn-in provides a way to improve throughput by eliminating weak product early in the manufacturing process.

摘要翻译： 在本发明中公开了一种在晶片级别对DRAM或FeRAM进行老化测试的方法。 在晶片级老化测试期间，在DRAM或FeRAM的所有存储电容器上施加应力电压以除去具有弱存储器单元的存储器芯片。 三个焊盘被添加到存储器芯片以适应老化信号，字线电压和应力电压。 老化信号禁用正常的存储器操作，对所有字线通电，并连接存储器单元的存储电容器之间的应力电压。 存储电容器两端的应力电压是外部施加的应力电压与通过字线连接到存储单元的位线的低电压之间的差异。 晶圆级老化提供了一种通过在制造过程早期消除弱产品来提高吞吐量的方法。