发明授权
US06333895B1 Clock synchronous semiconductor device having a reduced clock access time 失效
时钟同步半导体器件具有减小的时钟存取时间

  • 专利标题: Clock synchronous semiconductor device having a reduced clock access time
  • 专利标题(中): 时钟同步半导体器件具有减小的时钟存取时间
  • 申请号: US09678792
    申请日: 2000-10-04
  • 公开(公告)号: US06333895B1
    公开(公告)日: 2001-12-25
  • 发明人: Takeshi HamamotoSatoshi Kawasaki
  • 申请人: Takeshi HamamotoSatoshi Kawasaki
  • 优先权: JP11-286624 19991007
  • 主分类号: G11C800
  • IPC分类号: G11C800
Clock synchronous semiconductor device having a reduced clock access time
摘要:
In an output data control circuit for transferring complementary data signals read from a memory array to an external data output node in accordance with an output clock signal, a clocked gate circuit transferring complementary data signals in synchronization with an output clock signal and an output data latch circuit latching an output signal of the clocked gate circuit are operated using a voltage level not exceeding an internal power supply voltage, and the complementary data signals read from a memory cell is subjected to an amplitude expanding processing in a stage preceding the clocked gate circuit, and then is applied to the clocked gate circuit. A clock synchronous semiconductor memory device allowing reduction of a clock access time is provided.
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