发明授权
- 专利标题： Method of determining lethality of defects in circuit pattern inspection method of selecting defects to be reviewed and inspection system of circuit patterns involved with the methods
- 专利标题（中）： 确定电路图案检查缺陷检测方法的选择方法及其检查方法
-
申请号： US09225513申请日： 1999-01-06
-
公开(公告)号： US06334097B1公开(公告)日： 2001-12-25
- 发明人: Yasuhiro Yoshitake , Masataka Shiba , Atsushi Shimoda
- 申请人： Yasuhiro Yoshitake , Masataka Shiba , Atsushi Shimoda
- 优先权： JP10-010456 19980122
- 主分类号： G06F1132
- IPC分类号： G06F1132
摘要：
From the coordinate data of defects detected on the circuit patterns, the areas where the defects belong are identified. The sizes of the defects detected are compared with the data to determine the lethality to thereby determine the lethality of the defects. Further, the severity of the defects is calculated from the sizes of the defects to thereby select the review object in the descending order of the severity. Thereby, when inspecting the circuit patterns on a semiconductor wafer or the like, the lethality of the defects can automatically be determined even though the review is not carried out, enhancing the efficiency of the inspection. To perform the review with efficiency, the defects to be reviewed are automatically selected, while the quality of the inspection itself is maintained.
信息查询
