- 专利标题: Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
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申请号: US09824215申请日: 2001-04-03
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公开(公告)号: US06335251B1公开(公告)日: 2002-01-01
- 发明人: Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
- 申请人: Kiyotaka Miyano , Ichiro Mizushima , Yoshitaka Tsunashima , Tomohiro Saito
- 优先权: JP10-150211 19980529
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
A semiconductor apparatus on which a MOS transistor having an elevated source and drain structure is formed is arranged to have a gate electrode which is formed on the surface of a silicon substrate through an insulating film. An elevated source film and an elevated drain film each having at least a surface portion constituted by a metal silicide film, being conductive and elevated over the surface of the silicon substrate are formed on a source region and a drain region on the surface of the silicon substrate. Thus, a MOS transistor having a structure in which the surfaces of the source region and the drain region are elevated over the surface of the silicon substrate is formed. A first gate-side-wall insulating film is formed on the side wall of the gate electrode of the MOS transistor and having a bottom surface formed apart from the surface of the silicon substrate. A second gate-side-wall insulating film is formed between the first gate-side-wall insulating film and the gate electrode and on the bottom surface of the first gate-side-wall insulating film. The portion formed on the bottom surface exists in an inner bottom surface portion of the bottom surface of the first gate-sidewall insulating film adjacent to the gate electrode. The elevated source film and the elevated drain film are free from any facet in portions made contact with the first gate-side-wall insulating film.
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