发明授权
US06344759B1 Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation 有权
多米诺逻辑电路中的混合数据和时钟充电技术可以最大程度地降低评估过程中的电荷共享

  • 专利标题: Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation
  • 专利标题(中): 多米诺逻辑电路中的混合数据和时钟充电技术可以最大程度地降低评估过程中的电荷共享
  • 申请号: US09420160
    申请日: 1999-10-18
  • 公开(公告)号: US06344759B1
    公开(公告)日: 2002-02-05
  • 发明人: Pranjal SrivastavaPatrick W. BosshartUming Ko
  • 申请人: Pranjal SrivastavaPatrick W. BosshartUming Ko
  • 主分类号: H03K19096
  • IPC分类号: H03K19096
Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation
摘要:
A domino logic circuit includes a precharge device precharging a precharge node during a precharge phase and a logic block receiving plural input signals to conditionally discharge the precharge node. In this improvement a second precharge device precharges an intermediate node when a particular input signal controls its corresponding logic device to be nonconducting. The intermediate node precharged by this second precharge device may be any intermediate node including the last in a serial chain from the precharge node. This second precharge device may be used with a third precharge device according to the prior art which precharges the intermediate node during the precharge phase. This domino logic circuit may be used with another precharge device controlled by a second input signal different from the first input signal. This additional precharge device may be used to precharge the same intermediate node or another intermediate node. If the input signal controlling the second precharge device is unconstrained, then the circuit preferably includes a clock controlled precharge device to precharge the intermediate node during the precharge phase and a discharge control device disposed between said logic block and ground preventing discharge during the precharge phase. Alternatively, the input signal may be clocked and guaranteed low during the precharge phase. In this case, the clocked precharge of the intermediate node and the discharge control device are optional.
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