发明授权
US06347367B1 Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures 失效
用于多存储器存储和驱动器接收器技术的数据总线结构以及操作这种结构的方法

  • 专利标题: Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures
  • 专利标题(中): 用于多存储器存储和驱动器接收器技术的数据总线结构以及操作这种结构的方法
  • 申请号: US09240647
    申请日: 1999-01-29
  • 公开(公告)号: US06347367B1
    公开(公告)日: 2002-02-12
  • 发明人: Timothy J. DellSteven A. GrundonMark W. Kellogg
  • 申请人: Timothy J. DellSteven A. GrundonMark W. Kellogg
  • 主分类号: G06F1200
  • IPC分类号: G06F1200
Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures
摘要:
The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.3V) receiver/driver circuits and double rate (DDR) receiver/driver circuits, with an identification circuit for identifying the type of DIMMs in the memory system coupled thereto, a selection circuit for selecting the receiver/driver circuits required to access the identified DIMMs, and switch for adding or removing terminations to the data query lines, interconnecting the selected receiver driver circuits to identified DIMMS. Thus the invention provides a memory system that can access either 3.3V DIMMs or DDR DIMMs and automatically provide the proper terminations on the data bus used to access the DIMMs.
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