发明授权
US06351803B2 Mechanism for power efficient processing in a pipeline processor 失效
管道处理器中功率效率处理的机制

  • 专利标题: Mechanism for power efficient processing in a pipeline processor
  • 专利标题(中): 管道处理器中功率效率处理的机制
  • 申请号: US09410929
    申请日: 1999-10-01
  • 公开(公告)号: US06351803B2
    公开(公告)日: 2002-02-26
  • 发明人: Chih-Jui PengLew Chua-Eoan
  • 申请人: Chih-Jui PengLew Chua-Eoan
  • 主分类号: G06F930
  • IPC分类号: G06F930
Mechanism for power efficient processing in a pipeline processor
摘要:
A processor including a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. A pipefile having at least the same number of entries as the number of execution pipeline stages is included in the processor. A pointer register is associated with each execution pipeline stage. A value is stored in at least one of the pointer registers, the value indicating a particular one of the entries in the pipefile.
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