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26 条记录 (耗时 0.016 秒)

    Address translator and method of operation
    1.
    发明授权
    Address translator and method of operation 失效
    地址转换器和操作方法

    公开(公告)号：US5530822A

    公开(公告)日：1996-06-25

    申请号：US223067

    申请日：1994-04-04

    申请人： Brad Beavers ,  Lew Chua-Eoan ,  Chih-Jui Peng

    发明人： Brad Beavers ,  Lew Chua-Eoan ,  Chih-Jui Peng

    IPC分类号： G06F12/10 ,  G11C15/00

    CPC分类号： G06F12/1036

    摘要： An address translator (126) translates addresses, acting like a register file or a table, as necessary. The address translator contains a number of entries for matching an input address to a stored tag. An entry outputs a stored translated address if its stored tag matches the input address. A decoder (138) selects a particular entry in which to store an input translated address when the address translator operates as a register file. In these cases, a register number is also stored in the particular entry's as the entry's tag. Later, when it is necessary to read the particular entry, the register number is compared to each entry's tag to find a match. The disclosed address translator is compatible with both hardware and software refill algorithms ("tablewalks") without impacting its critical read speed path.

    摘要翻译： 地址转换器（126）根据需要翻译地址，像寄存器文件或表格一样。 地址转换器包含一些用于将输入地址与存储标签进行匹配的条目。 如果存储的标签与输入地址匹配，则输入输出存储的翻译地址。 当地址转换器作为寄存器文件操作时，解码器（138）选择存储输入转换地址的特定条目。 在这些情况下，寄存器编号也作为条目的标签存储在特定条目中。 稍后，当需要读取特定条目时，将寄存器编号与每个条目的标签进行比较以找到匹配项。 所公开的地址转换器与硬件和软件补充算法（“台式”）兼容，而不影响其关键的读取速度路径。

    Mechanism for power efficient processing in a pipeline processor
    2.
    发明授权
    Mechanism for power efficient processing in a pipeline processor 失效
    管道处理器中功率效率处理的机制

    公开(公告)号：US06351803B2

    公开(公告)日：2002-02-26

    申请号：US09410929

    申请日：1999-10-01

    申请人： Chih-Jui Peng ,  Lew Chua-Eoan

    发明人： Chih-Jui Peng ,  Lew Chua-Eoan

    IPC分类号： G06F930

    CPC分类号： G06F9/3836 ,  G06F9/3824 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

    摘要： A processor including a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. A pipefile having at least the same number of entries as the number of execution pipeline stages is included in the processor. A pointer register is associated with each execution pipeline stage. A value is stored in at least one of the pointer registers, the value indicating a particular one of the entries in the pipefile.

    摘要翻译： 一种处理器，包括多个执行流水线级，其中每个级接受多个操作数输入并产生结果。 具有与执行流水线级数相同数量的条目的管道文件包括在处理器中。 指针寄存器与每个执行流水线阶段相关联。 一个值存储在至少一个指针寄存器中，该值指示管道文件中特定的一个条目。

    Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
    3.
    发明授权
    Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline 失效
    使用连接到管道的单个管道文件在处理器管道中转发数据的机制

    公开(公告)号：US06633971B2

    公开(公告)日：2003-10-14

    申请号：US09411431

    申请日：1999-10-01

    申请人： Chih-Jui Peng ,  Lew Chua-Eoan

    发明人： Chih-Jui Peng ,  Lew Chua-Eoan

    IPC分类号： G06F934

    CPC分类号： G06F9/3875 ,  G06F9/3824 ,  G06F9/3826

    摘要： A method for forwarding data within a pipeline of a pipelined data processor having a plurality of execution pipeline stages where each stage accepts a plurality of operand inputs and generates a result. The result generated by each execution pipeline stage is selectively coupled to an operand input of one of the execution pipeline stages.

    摘要翻译： 一种用于在具有多个执行流水线级的流水线数据处理器的流水线内转发数据的方法，其中每个级接受多个操作数输入并产生结果。 每个执行流水线阶段生成的结果选择性地耦合到执行流水线阶段之一的操作数输入。

    Fully associative address translation buffer having separate segment and page invalidation
    4.
    发明授权
    Fully associative address translation buffer having separate segment and page invalidation 失效
    完全关联地址转换缓冲区具有单独的段和页面无效

    公开(公告)号：US5682495A

    公开(公告)日：1997-10-28

    申请号：US353007

    申请日：1994-12-09

    申请人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

    发明人： Brad B. Beavers ,  Lew Chua-Eoan ,  Pei-Chun Peter Liu ,  Chih-Jui Peng

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1036

    摘要： A fully associative address translator which includes a number of entries, each of said number of entries translating a received effective address into a real address, each received effective address including a segment identifier and a page identifier. Each of the entries within the fully associative address translator includes a first translation from an effective address segment identifier into a virtual address segment identifier and a second translation from a virtual address page identifier to a real address page identifier. A first valid bit cell is provided for storing a validity bit which indicates the validity of the first translation from the effective address segment identifier to the virtual address segment identifier and a second valid bit cell is also provided for storing a validity bit indicating the validity of the second translation from the virtual address page identifier to the real address page identifier wherein a process context switch will invalidate only a portion of each of the entries, thereby reducing the miss penalty associated with a context switch.

    摘要翻译： 一种完全关联地址转换器，其包括多个条目，所述数量的条目中的每一个将接收的有效地址转换为实际地址，每个接收到的有效地址包括段标识符和页面标识符。 完全关联地址转译器中的每个条目包括从有效地址段标识符到虚拟地址段标识符的第一转换和从虚拟地址页标识符到真实地址页标识符的第二转换。 提供第一有效比特单元，用于存储指示从有效地址段标识符到虚拟地址段标识符的第一翻译的有效性的有效位，并且还提供第二有效位单元，用于存储指示有效位的有效位 从虚拟地址页标识符到实际地址页标识符的第二转换，其中处理上下文切换将仅使每个条目的一部分无效，从而减少与上下文切换相关联的未命中。

    Adaptive voltage scaling for an electronics device
    6.
    发明申请
    Adaptive voltage scaling for an electronics device 有权
    电子设备的自适应电压调整

    公开(公告)号：US20070096775A1

    公开(公告)日：2007-05-03

    申请号：US11286087

    申请日：2005-11-22

    申请人： Mohamed Elgebaly ,  Khurram Malik ,  Lew Chua-Eoan ,  Seong-Ook Jung

    发明人： Mohamed Elgebaly ,  Khurram Malik ,  Lew Chua-Eoan ,  Seong-Ook Jung

    IPC分类号： H03B21/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： Techniques for adaptively scaling voltage for a processing core are described. In one scheme, the logic speed and the wire speed for the processing core are characterized, e.g., using a ring oscillator having multiple signal paths composed of different circuit components. A target clock frequency for the processing core is determined, e.g., based on computational requirements for the core. A replicated critical path is formed based on the characterized logic speed and wire speed and the target clock frequency. This replicated critical path emulates the actual critical path in the processing core and may include different types of circuit components such as logic cells with different threshold voltages, dynamic cells, bit line cells, wires, drivers with different threshold voltages and/or fan-outs, and so on. The supply voltage for the processing core and the replicated critical path is adjusted such that both achieve the desired performance.

    摘要翻译： 描述了用于自适应地缩放处理核心的电压的技术。 在一种方案中，处理核心的逻辑速度和线速度的特征在于，例如使用具有由不同电路部件组成的多个信号路径的环形振荡器。 例如，基于对核心的计算要求来确定处理核心的目标时钟频率。 基于特征逻辑速度和线速度和目标时钟频率形成复制关键路径。 该复制的关键路径模拟处理核心中的实际关键路径，并且可以包括不同类型的电路组件，例如具有不同阈值电压的逻辑单元，动态单元，位线单元，电线，具有不同阈值电压的驱动器和/或扇出 ， 等等。 调整处理核心和复制关键路径的电源电压，使得两者都达到期望的性能。

    Apparatus and method for relative position annotation of standard cell components to facilitate datapath design
    7.
    发明授权
    Apparatus and method for relative position annotation of standard cell components to facilitate datapath design 有权
    用于标准单元组件的相对位置注释以便于数据通路设计的装置和方法

    公开(公告)号：US06883156B1

    公开(公告)日：2005-04-19

    申请号：US10159818

    申请日：2002-05-31

    申请人： Alex Khainson ,  Donald C. Ramsey, Jr. ,  Lew Chua-Eoan ,  Era K. Nangia

    发明人： Alex Khainson ,  Donald C. Ramsey, Jr. ,  Lew Chua-Eoan ,  Era K. Nangia

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5072

    摘要： A method of designing a circuit includes annotating relative positions of instantiated hierarchical macro cells, which include two or more instantiated standard cells. The relative positions of individual instantiated standard cells may also be annotated. Relative positions of instantiated hierarchical macro cells and individual instantiated standard cells may be altered to form a more compact standard cell configuration. Pin positions may also be annotated by relative position. Relative pin positions may be altered to promote dense signal line routing within the standard cell design. The relative positions of the instantiated hierarchical macro cells and individual instantiated standard cells are converted to absolute grid position locations to form a grid assigned circuit. The grid assigned circuit is then routed.

    摘要翻译： 设计电路的方法包括注释实例化的分层宏小区的相对位置，其包括两个或多个实例化的标准小区。 单个实例化标准单元的相对位置也可以被注释。 可以改变实例化的分级宏小区和各个实例化的标准小区的相对位置以形成更紧凑的标准小区配置。 针位置也可以由相对位置注释。 可以改变相对引脚位置以促进标准单元设计内的密集信号线路由。 实例化的分级宏小区和单独实例化的标准小区的相对位置被转换为绝对网格位置位置，以形成网格分配电路。 然后路由网格分配电路。

    Full scan solution for latched-based design
    9.
    发明授权
    Full scan solution for latched-based design 有权
    全扫描解决方案，用于基于锁存的设计

    公开(公告)号：US07543207B2

    公开(公告)日：2009-06-02

    申请号：US11764137

    申请日：2007-06-15

    申请人： Lew Chua-Eoan ,  Era Kasturia Nangia

    发明人： Lew Chua-Eoan ,  Era Kasturia Nangia

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318544 ,  G01R31/318536 ,  G01R31/318541

    摘要： A full-scan latch is provided that may be used to incorporate design for test functionality in an integrated circuit. The full-scan latch includes a shadow latch, a multiplexer, and a slave latch. The full-scan latch has a test mode and a normal mode. When in the normal mode, the device operates as a transparent latch, passing a data input to its output. When in test mode, the device is operable to pass scan data down a scan chain and to inject scan data into the data path.

    摘要翻译： 提供了全扫描锁存器，可以将其用于集成电路中的测试功能的设计。 全扫描锁存器包括阴影锁存器，复用器和从锁存器。 全扫描锁存器具有测试模式和正常模式。 当处于正常模式时，器件作为透明锁存器工作，将数据输入传送到其输出端。 当处于测试模式时，该设备可操作地将扫描数据沿着扫描链传递并将扫描数据注入到数据路径中。

    Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals
    10.
    发明申请
    Method and apparatus for controlling the flow of data between two circuits by generating one or more phase shifted clock signals 失效
    用于通过产生一个或多个相移时钟信号来控制两个电路之间的数据流的方法和装置

    公开(公告)号：US20060085662A1

    公开(公告)日：2006-04-20

    申请号：US11292844

    申请日：2005-12-01

    申请人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

    发明人： Lew Chua-Eoan ,  Atsushi Hasegawa ,  Hsuan-Wen Wang

    IPC分类号： G06F1/04

    CPC分类号： G06F5/06 ,  G06F1/06

    摘要： An interface circuit according to one embodiment of the present invention includes a clock signal, a first phase locked loop coupled to the clock signal line and generating a reference clock signal, a second phase locked loop receiving the reference clock signal, and in accordance therewith, generating one or more phase shifted reference clock signals, and a data transceiver circuit coupled to receive at least one of the clock signal, the reference clock signal, or one or more of the phase shifted reference clock signals to control the flow of data between a first circuit and a second circuit. An interface circuit according to one embodiment of the invention can be used advantageously for controlling the flow of data between a CPU and an external memory.

    摘要翻译： 根据本发明的一个实施例的接口电路包括时钟信号，耦合到时钟信号线并产生参考时钟信号的第一锁相环，接收参考时钟信号的第二锁相环， 产生一个或多个相移参考时钟信号，以及数据收发器电路，其耦合以接收所述时钟信号，所述参考时钟信号或所述相移基准时钟信号中的至少一个，以控制所述相移参考时钟信号之间的数据流 第一电路和第二电路。 根据本发明的一个实施例的接口电路可以有利地用于控制CPU和外部存储器之间的数据流。