发明授权
US06374333B1 Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention
失效
缓存一致性协议,其中使用加载指令提示位来指示由干预提供的修改的高速缓存行的释放
- 专利标题: Cache coherency protocol in which a load instruction hint bit is employed to indicate deallocation of a modified cache line supplied by intervention
- 专利标题(中): 缓存一致性协议,其中使用加载指令提示位来指示由干预提供的修改的高速缓存行的释放
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申请号: US09437176申请日: 1999-11-09
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公开(公告)号: US06374333B1公开(公告)日: 2002-04-16
- 发明人: Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
- 申请人: Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
- 主分类号: G06F1200
- IPC分类号: G06F1200
摘要:
A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.
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