-
公开(公告)号：US08754546B2
公开(公告)日：2014-06-17
申请号：US12425275
申请日：2009-04-16
Applicant: Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Steven John Ahladas
IPC: H02J1/00
CPC classification number: H05K7/1492 , H02J1/102 , Y10T307/344 , Y10T307/352 , Y10T307/391 , Y10T307/406 , Y10T307/62 , Y10T307/707
Abstract: A bulk power assembly includes a bulk power distribution (BPD) subassembly and a bulk power controller and hub (BPCH) subassembly coupled to the BPD subassembly. The BPD assembly is configured to provide bulk DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the DC bulk power. The BPCH subassembly is configured to monitor and control the BPD assembly.
Abstract translation: 散装电源组件包括耦合到BPD子组件的大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPD组件配置为从交流输入电源和直流输入电源提供批量直流电源。 BPD子组件配置为分配DC大容量电源。 BPCH子组件被配置为监视和控制BPD组件。
-
公开(公告)号：US20100269119A1
公开(公告)日：2010-10-21
申请号：US12424893
申请日：2009-04-16
Applicant: Ravi Kumar Arimilli , Piyush Chaudhary
Inventor： Ravi Kumar Arimilli , Piyush Chaudhary
IPC: G06F9/46
CPC classification number: G06F9/5011 , G06F9/5061
Abstract: Disclosed are a method, a system and a computer program product for automatically allocating and de-allocating resources for jobs executed or processed by one or more supercomputer systems. In one or more embodiments, a supercomputing system can process multiple jobs with respective supercomputing resources. A global resource manager can automatically allocate additional resources to a first job and de-allocate resources from a second job. In one or more embodiments, the global resource manager can provide the de-allocated resources to the first job as additional supercomputing resources. In one or more embodiments, the first job can use the additional supercomputing resources to perform data analysis at a higher resolution, and the additional resources can compensate for an amount of time the higher resolution analysis would take using originally allocated supercomputing resources.
Abstract translation: 公开了一种用于为由一个或多个超级计算机系统执行或处理的作业自动分配和分配资源的方法，系统和计算机程序产品。 在一个或多个实施例中，超级计算系统可以使用相应的超级计算资源处理多个作业。 全局资源管理器可以自动为第一个作业分配额外的资源，并从第二个作业中分配资源。 在一个或多个实施例中，全局资源管理器可以将去分配的资源作为附加的超级计算资源提供给第一作业。 在一个或多个实施例中，第一作业可以使用额外的超级计算资源以更高的分辨率执行数据分析，并且附加资源可以补偿使用原始分配的超级计算资源的更高分辨率分析所花费的时间量。
-
公开(公告)号：US20100264731A1
公开(公告)日：2010-10-21
申请号：US12425267
申请日：2009-04-16
Applicant: Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
Inventor： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Covi , Gerald J. Fahr , Daniel James Barus
IPC: H02J4/00
CPC classification number: H02J1/102 , Y10T307/352 , Y10T307/707
Abstract: A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
Abstract translation: 电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。
-
公开(公告)号：US07783842B2
公开(公告)日：2010-08-24
申请号：US10339764
申请日：2003-01-09
Applicant: Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
Inventor： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC: G06F12/00
CPC classification number: G06F12/0835
Abstract: A processing unit includes a processor core, an input/output (I/O) communication adapter coupled to the processor core, and a cache system coupled to the processor core and to the I/O communication adapter. The cache system including a cache array, a cache directory and a cache controller. The cache controller snoops I/O communication by the I/O communication adapter and, in response to snooping the I/O communication adapter performing an I/O data write of outgoing data in an exclusive state, invalidates corresponding data stored within the cache array.
Abstract translation: 处理单元包括处理器核心，耦合到处理器核心的输入/输出（I / O）通信适配器以及耦合到处理器核心和I / O通信适配器的高速缓存系统。 缓存系统包括缓存阵列，缓存目录和高速缓存控制器。 缓存控制器通过I / O通信适配器监听I / O通信，并且响应于窥探I / O通信适配器以独占状态执行输出数据的I / O数据写入，使存储在高速缓存阵列中的对应数据无效 。
-
5.发明申请公开(公告)号：US20100153965A1
公开(公告)日：2010-06-17
申请号：US12336302
申请日：2008-12-16
Applicant: Lakshminarayana Baba Arimilli , Ravi Kumar Arimilli , Claude Basso , Jean L. Calvignac
IPC: G06F9/46
CPC classification number: G06F9/4856 , G06F9/5066 , G06F9/5088
Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring communication between threads assigned to multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more of the threads are moved to a different one of the multiple processors based on the communication between the threads.
Abstract translation: 用于操作高性能计算（HPC）集群的技术包括监视分配给HPC集群中包括的多个处理器的线程之间的通信。 HPC集群包括多个节点，每个节点包含多个处理器中的两个或多个。 基于线程之间的通信将一个或多个线程移动到多个处理器中的不同的一个。
-
Patent Agency Ranking
6.发明授权Method and data processing system for processor-to-processor communication in a clustered multi-processor system 失效用于集群多处理器系统中处理器到处理器通信的方法和数据处理系统公开(公告)号：US07734877B2
公开(公告)日：2010-06-08
申请号：US11954686
申请日：2007-12-12
Applicant: Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC: G06F13/00
CPC classification number: G06F15/173 , H04W28/14
Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
Abstract translation: 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
-
7.发明申请Enhanced Processor Virtualization Mechanism Via Saving and Restoring Soft Processor/System States 失效通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制公开(公告)号：US20090157945A1
公开(公告)日：2009-06-18
申请号：US12352462
申请日：2009-01-12
Applicant: Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
Inventor： Ravi Kumar Arimilli , Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
CPC classification number: G06F9/30123 , G06F9/30116 , G06F9/3013 , G06F9/462
Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.
Abstract translation: 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。
-
8.发明授权System and method for completing full updates to entire cache lines stores with address-only bus operations 有权使用仅地址总线操作完成对整个高速缓存行存储的完全更新的系统和方法公开(公告)号：US07493446B2
公开(公告)日：2009-02-17
申请号：US12034769
申请日：2008-02-21
Applicant: Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
Inventor： Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
IPC: G06F12/12
CPC classification number: G06F12/0897 , G06F12/0804
Abstract: A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
Abstract translation: 一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。 处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。 当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。 由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失时或在RC机器获得写入许可之前数据进入状态时，不会检索高速缓存行的数据。
-
9.发明申请METHOD AND DATA PROCESSING SYSTEM FOR PROCESSOR-TO-PROCESSOR COMMUNICATION IN A CLUSTERED MULTI-PROCESSOR SYSTEM 失效集成多处理器系统中处理器到处理器通信的方法和数据处理系统公开(公告)号：US20080155231A1
公开(公告)日：2008-06-26
申请号：US11954686
申请日：2007-12-12
Applicant: Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
CPC classification number: G06F15/173 , H04W28/14
Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
Abstract translation: 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
-
10.发明授权Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network 有权基于群集的多处理器无线网络中微处理器通信的方法和数据处理系统公开(公告)号：US07360067B2
公开(公告)日：2008-04-15
申请号：US10318513
申请日：2002-12-12
Applicant: Ravi Kumar Arimilli , Robert Alan Cargnoni , Derek Edward Williams , Kenneth Lee Wright
IPC: G06F15/173
CPC classification number: G06F15/173 , H04W28/14
Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the processor cluster network by providing processor communications to be immediately networked and transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.
Abstract translation: 包含在多处理器集群网络内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有在群集网络内的每个PCR内存储到扇区的专有权限，并且具有连续访问以读取其自己的PCR的内容。 每个处理器通过专用协议或专用无线网络在所有PCR内更新其独占部分，立即允许集群网络内的所有其他处理器在PCR数据中查看变化，并绕过缓存子系统。 处理器集群网络中的效率得到提高，通过提供处理器通信来立即联网并传输到所有处理器中，而不会立即限制对信息的访问，或迫使所有处理器持续竞争相同的高速缓存线，从而压倒互连和内存 系统具有无限的加载流，存储和无效命令。
-
-
-
-
-
-
-
-
-
Search Results
370
records
(took 0.024 seconds)
