Invention Grant
- Patent Title: Method for manufacturing a semiconductor device
- Patent Title (中): 半导体器件的制造方法
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Application No.: US09669896Application Date: 2000-09-27
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Publication No.: US06376331B1Publication Date: 2002-04-23
- Inventor: Minoru Higuchi
- Applicant: Minoru Higuchi
- Priority: JP9-021593 19970204
- Main IPC: H01L2176
- IPC: H01L2176

Abstract:
A semiconductor device is herein disclosed which comprises a plurality of element regions formed on a first conductive type semiconductor substrate, element isolation regions for isolating the element regions from each other, and gate electrodes on parts of the element regions, the element regions being in contact with the element isolation regions at side surfaces of the element regions, wherein in the element region under each gate electrode, the concentration of a first conductive type impurity is high in an element region top surface edge area (in the vicinity of 66), and on the side surfaces of each element region, except the portions under the gate electrode, the concentration of the first conductive type impurity is equal to or lower than that of the first conductive type impurity in the body of the element region. According to the present invention, in the semiconductor device having a trench isolation, the formation of a parasitic channel at element region top surface edges under a gate electrode can be prevented and a leak current in an OFF state can be reduced without any increase in a junction capacitance which retards the driving velocity of elements and without any increase in a junction leak current.
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