发明授权
US06376924B1 Position check mark 失效
位置复选标记

  • 专利标题: Position check mark
  • 专利标题(中): 位置复选标记
  • 申请号: US09484066
    申请日: 2000-01-18
  • 公开(公告)号: US06376924B1
    公开(公告)日: 2002-04-23
  • 发明人: Kazuo TomitaAtsushi Ueno
  • 申请人: Kazuo TomitaAtsushi Ueno
  • 优先权: JP11-206305 19990721
  • 主分类号: H01L23544
  • IPC分类号: H01L23544
Position check mark
摘要:
A mark structure (100) consists of a gate oxide film (102) formed on a semiconductor substrate (101), a gate wiring layer (103) formed on the gate oxide film (102), an insulating film (104) formed on the gate wiring layer (103) and a sidewall (105) formed in contact with side surfaces of the insulating film (104), the gate wiring layer (103) and the gate oxide film (102). An opaque bit line layer (113) is formed of a polycide consisting of a doped polysilicon layer (1131) and a tungsten silicide layer (1132), extending from on the interlayer insulating film (107) to on the mark structure (100). With this structure, a semiconductor device which allows measurement of alignment mark and overlay check mark with high precision in a lithography process, has no structure unnecessary for a mark and suppresses creation of extraneous matter in a process of manufacturing a semiconductor device to prevent deterioration in manufacturing process yield and a method of manufacturing the semiconductor device can be provided.
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