A manufacturing process including: forming a substrate and insulating layer including a tunnel area; and simultaneously forming a floating gate region of a memory transistor and a lower gate portion of a selection transistor, the floating gate region internally forming a hole, one side of which delimits, together with an external side of the floating gate region, a portion of tunnel arranged above the tunnel area; a dielectric material layer is then deposited, and fills the hole of the floating gate region; the structure is planarized by CMP, and an insulating region of dielectric material is formed; and a control gate region is formed above the floating gate region and simultaneously an upper gate portion is formed above the lower gate portion. The upper and lower gate portions form a control gate region of the selection transistor. In this way, the upper gate portion and the control gate region are substantially on the same level.