公开(公告)号：US06501147B1

公开(公告)日：2002-12-31

申请号：US09713144

申请日：2000-11-14

申请人： Bruno Vajana ,  Matteo Patelmo

发明人： Bruno Vajana ,  Matteo Patelmo

IPC分类号： H01L2900

CPC分类号： H01L27/11526 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

摘要： A process for manufacturing an electronic device having an HV MOS transistor with a low multiplication coefficient and a high threshold in a non-implanted area of the substrate, this area having the same conductivity type and the same doping level as the substrate. The transistor is obtained by forming, over the non-implanted substrate area, a first gate region of semiconductor material having the same doping type as the non-implanted substrate area; and forming, inside the non-implanted substrate area, first source and drain regions of a second conductivity type, arranged at the sides of the first gate region. At the same time, a dual-gate HV MOS transistor is formed, the source and drain regions of which are housed in a tub formed in the substrate and having the first conductivity type, but at a higher concentration than the non-implanted substrate area. It is moreover possible to form a nonvolatile memory cell simultaneously in a second tub of the substrate of semiconductor material.

摘要翻译： 一种用于制造具有在衬底的非注入区域中具有低倍增系数和高阈值的HV MOS晶体管的电子器件的方法，该区域具有与衬底相同的导电类型和相同的掺杂水平。 通过在非植入衬底区域上形成具有与非植入衬底区域相同的掺杂类型的半导体材料的第一栅极区域来获得晶体管; 以及在所述非植入衬底区域内形成布置在所述第一栅极区域侧面的第二导电类型的第一源极和漏极区域。 同时，形成双栅极HV MOS晶体管，其源极和漏极区域被容纳在形成在衬底中的具有第一导电类型的桶中，但是具有比未植入衬底区域更高的浓度 。 此外，可以在半导体材料的基板的第二槽中同时形成非易失性存储单元。

公开(公告)号：US06380034B1

公开(公告)日：2002-04-30

申请号：US09619861

申请日：2000-07-20

申请人： Bruno Vajana ,  Giovanna Dalla Libera

发明人： Bruno Vajana ,  Giovanna Dalla Libera

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42324

摘要： A manufacturing process including: forming a substrate and insulating layer including a tunnel area; and simultaneously forming a floating gate region of a memory transistor and a lower gate portion of a selection transistor, the floating gate region internally forming a hole, one side of which delimits, together with an external side of the floating gate region, a portion of tunnel arranged above the tunnel area; a dielectric material layer is then deposited, and fills the hole of the floating gate region; the structure is planarized by CMP, and an insulating region of dielectric material is formed; and a control gate region is formed above the floating gate region and simultaneously an upper gate portion is formed above the lower gate portion. The upper and lower gate portions form a control gate region of the selection transistor. In this way, the upper gate portion and the control gate region are substantially on the same level.

摘要翻译： 一种制造方法，包括：形成包括隧道区域的基板和绝缘层; 并且同时形成选择晶体管的存储晶体管和下栅极部分的浮动栅极区域，浮动栅极区域内部形成一个孔，其一侧与浮动栅极区域的外侧一起限定一部分 隧道布置在隧道以上; 然后沉积介电材料层，并填充浮栅区域的孔; 通过CMP对该结构进行平面化，形成介电材料的绝缘区域; 并且在浮置栅极区域的上方形成控制栅极区域，同时在下部栅极部分的上方形成上部栅极部分。 上部和下部栅极部分形成选择晶体管的控制栅极区域。 以这种方式，上部栅极部分和控制栅极区域基本上处于相同的电平。

公开(公告)号：US06307229B2

公开(公告)日：2001-10-23

申请号：US09081881

申请日：1998-05-19

申请人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

发明人： Nicola Zatelli ,  Federico Pio ,  Bruno Vajana

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device structure having a matrix of memory cells in a semiconductor material layer. The memory cells are located at intersections of rows and columns of the matrix. Each memory cell includes a control gate electrode connected to one of the rows, a first electrode connected to one of the columns and a second electrode. The rows comprise polysilicon strips extending parallel to each other in a first direction, and the columns are formed by metal strips extending parallel to each other in a second direction orthogonal to the first direction. Short-circuit metal strips are coupled for short-circuiting the second electrodes of the memory cells. The columns and the short-circuit strips arc respectively formed in a first metal level and a second metal level superimposed on each other and electrically insulated by a dielectric layer.

摘要翻译： 一种具有半导体材料层中的存储单元矩阵的非易失性半导体存储器件结构。 存储单元位于矩阵的行和列的交点处。 每个存储单元包括连接到行中的一个的控制栅电极，连接到一列的第一电极和第二电极。 这些行包括在第一方向上彼此平行延伸的多晶硅条，并且所述列由在与第一方向正交的第二方向上彼此平行延伸的金属条形成。 短路金属带被耦合以使存储器单元的第二电极短路。 列和短路带分别形成在第一金属层和第二金属层之间，第二金属层与第二金属层叠在一起，并被电介质层电绝缘。

公开(公告)号：US5985718A

公开(公告)日：1999-11-16

申请号：US996922

申请日：1997-12-23

申请人： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

发明人： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A process for fabricating a memory cell having two levels of polysilicon and being included in a memory device of the EEPROM type, wherein the device is formed on a semiconductor material substrate which has a first conductivity type. The process comprises the steps of forming, on the substrate a thin tunnel oxide region surrounded by a gate oxide region previously formed on the same substrate, depositing a layer of polycrystalline silicon over the gate oxide region and the thin tunnel oxide region, and successively depositing a composite ONO layer and an additional polysilicon layer over the polycrystalline silicon layer. A capacitive implant mask having a window is formed by depositing a layer of a light-sensitive material over the additional polysilicon layer, a dopant is implanted through the window at an energy and with dosages effective to penetrate the polycrystalline silicon, ONO, and polysilicon layers, respectively, and a region of electric continuity is formed laterally and beneath the thin tunnel oxide region.

摘要翻译： 一种用于制造具有两级多晶硅并且被包括在EEPROM类型的存储器件中的存储单元的工艺，其中该器件形成在具有第一导电类型的半导体材料衬底上。 该方法包括以下步骤：在衬底上形成由先前形成在同一衬底上的栅极氧化物区域围绕的薄的隧道氧化物区域，在栅极氧化物区域和薄的隧道氧化物区域上沉积多晶硅层，并依次沉积 多晶硅层上的复合ONO层和附加多晶硅层。 具有窗口的电容注入掩模通过在附加多晶硅层上沉积感光材料层而形成，通过窗口以能量注入掺杂剂并且具有有效穿透多晶硅，ONO和多晶硅层的剂量 并且在薄隧道氧化物区域的横向和下方形成电连续性区域。

公开(公告)号：US06576517B1

公开(公告)日：2003-06-10

申请号：US09474944

申请日：1999-12-30

申请人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

发明人： Matteo Patelmo ,  Giovanna Dalla Libera ,  Nadia Galbiati ,  Bruno Vajana

IPC分类号： H01L218234

CPC分类号： H01L27/112 ,  G11C11/56 ,  G11C11/5692 ,  H01L27/11293

摘要： Presented is a method for obtaining a multi-level ROM in a dual gate EEPROM process flow. The method begins with, on a semiconductor substrate, defining active areas respectively for transistors of ROM cells, transistors of electrically erasable non-volatile memory cells, and additional transistors of the storage circuitry. Then, integrated capacitors are integrated in the storage circuit. According to this method, during the implanting step for forming integrated capacitors, at least an active area of the ROM cell is similarly implanted.

摘要翻译： 提出了一种在双栅极EEPROM工艺流程中获得多级ROM的方法。 该方法开始于在半导体衬底上分别为ROM单元的晶体管，电可擦除非易失性存储单元的晶体管和存储电路的附加晶体管分别定义有效区域。 然后，集成电容器集成在存储电路中。 根据该方法，在用于形成集成电容器的注入步骤期间，类似地植入ROM单元的至少有效区域。

公开(公告)号：US06528885B2

公开(公告)日：2003-03-04

申请号：US09968682

申请日：2001-10-01

申请人： Bruno Vajana ,  Matteo Patelmo

发明人： Bruno Vajana ,  Matteo Patelmo

IPC分类号： H01L2348

CPC分类号： H01L27/0203 ,  G06K19/073 ,  H01L21/768 ,  H01L23/522 ,  H01L23/573 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making an integrated circuit that is resistant to an unauthorized duplication through reverse engineering includes forming a plurality of false contacts and/or false interconnection vias in the integrated circuit. These false contacts and/or false interconnection vias are connected as true contacts and true interconnection vias by lines patterned in a metallization layer deposited over an insulating dielectric layer or multilayer through which the true contacts and/or the true interconnection vias are formed. False contacts and false vias extend in the respective dielectric layers or multilayers to a depth insufficient to reach the active areas of a semiconductor substrate for false contacts, or to a depth insufficient to reach a layer of conductive material below the dielectric layers or multilayers for false interconnection vias.

摘要翻译： 通过逆向工程制造抗未授权复制的集成电路的方法包括在集成电路中形成多个假触点和/或伪互连通孔。 这些假触点和/或伪互连通孔通过在沉积在绝缘介电层或多层上的金属化层中图案化的线连接为真实触点和真实的互连通孔，绝缘介电层或多层通过其形成真实的触点和/或真实的互连通孔。 假触点和假通孔在相应的电介质层或多层中延伸到不足以到达用于错误接触的半导体衬底的有源区的深度，或者到达不足以达到介电层或多层下方的导电材料层的深度为假 互连通孔

公开(公告)号：US06432762B1

公开(公告)日：2002-08-13

申请号：US09534253

申请日：2000-03-23

申请人： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

发明人： Giovanna Dalla Libera ,  Bruno Vajana ,  Roberta Bottini ,  Carlo Cremonesi

IPC分类号： H01L218238

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： A memory cell for devices of the EEPROM type, formed in a portion of a semiconductor material substrate having a first conductivity type. The memory cell includes source and drain regions having a second conductivity type and extending at the sides of a gate oxide region which includes a thin tunnel oxide region. The memory cell also includes a region of electric continuity having the second conductivity type, being formed laterally and beneath the thin tunnel oxide region, and partly overlapping the drain region, and a channel region extending between the region of electric continuity and the source region. The memory cell further includes an implanted region having the first conductivity type and being formed laterally and beneath the gate oxide region and incorporating the channel region.

摘要翻译： 用于EEPROM型器件的存储单元，形成在具有第一导电类型的半导体材料衬底的一部分中。 存储单元包括具有第二导电类型的源极和漏极区域，并且在包括薄的隧道氧化物区域的栅极氧化物区域的侧面延伸。 存储单元还包括具有第二导电类型的电连续性区域，横向形成在薄隧道氧化物区域下方，并且部分地与漏极区域重叠，以及在电连通区域和源极区域之间延伸的沟道区域。 存储单元还包括具有第一导电类型并且横向形成在栅极氧化物区域下方并且结合沟道区域的注入区域。

公开(公告)号：US06194270B1

公开(公告)日：2001-02-27

申请号：US09130720

申请日：1998-08-06

申请人： Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Carlo Cremonesi

发明人： Roberta Bottini ,  Giovanna Dalla Libera ,  Bruno Vajana ,  Carlo Cremonesi

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： Process for manufacturing an electrically programmable non-volatile memory device having electrically programmable non-volatile memory cells comprising floating-gate MOS transistors, a first kind of MOSFETs, and a second kind of MOSFETs capable of substaining gate voltages higher than that sustainable by the MOSFETs of the first kind. The process includes forming a first gate oxide layer for the floating-gate MOS transistors, a second gate oxide layer for the MOSFETs of the first kind, and a third gate oxide layer for the MOSFETs of the second kind. The first gate oxide layer further comprises a tunnel oxide region. The process provides for: forming over the surface of a semiconductor material a first layer of oxide; selectively removing the first layer of oxide from regions of said surface dedicated to the MOSFETs of the first kind, but not from the regions dedicated to the floating-gate MOS transistors nor to the MOSFETs of the second kind; forming a second layer of oxide over the first layer of oxide and over said regions dedicated to the MOSFETs of the first kind; simultaneously removing the first and the second layer of oxide only from the tunnel oxide region of the floating-gate MOS transistors; and forming over the second layer of oxide and over said tunnel region oxide for the floating-gate MOS transistors a tunnel oxide layer. The third gate oxide layer and said first gate oxide layer, except in the tunnel oxide region, are formed by the superposition of the first layer of oxide, while the second layer of oxide and the tunnel oxide layer, said second gate oxide layer being formed by the superposition of the second layer of oxide and the tunnel oxide layer.

摘要翻译： 用于制造具有电可编程非易失性存储单元的电可编程非易失性存储器件的方法，所述非易失性存储器单元包括浮置栅极MOS晶体管，第一种MOSFET和能够将栅极电压高于由MOSFET可持续的栅极电压的第二种MOSFET 的第一种。 该工艺包括形成用于浮置栅极MOS晶体管的第一栅极氧化物层，用于第一种MOSFET的第二栅极氧化物层和用于第二种MOSFET的第三栅极氧化物层。 第一栅极氧化物层还包括隧道氧化物区域。 该方法提供：在半导体材料的表面上形成第一层氧化物; 从专用于第一种MOSFET的所述表面的区域中，而不是从专用于浮栅MOS晶体管的区域到第二类MOSFET的区域中选择性地去除第一层氧化物; 在第一层氧化物上形成第二层氧化物，并在专用于第一类MOSFET的所述区域上形成第二层氧化物; 同时从浮栅MOS晶体管的隧道氧化物区域去除第一和第二层氧化物; 并在所述第二层氧化物上形成所述隧道区氧化物，以使所述浮栅MOS晶体管成为隧道氧化物层。 除隧道氧化物区域外的第三栅极氧化物层和第一栅极氧化物层通过第一层氧化物的叠加形成，而第二层氧化物和隧道氧化物层形成，所述第二栅极氧化物层形成 通过第二层氧化物和隧道氧化物层的叠加。

公开(公告)号：US5732012A

公开(公告)日：1998-03-24

申请号：US210595

申请日：1994-03-17

申请人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

发明人： Paolo Cappelletti ,  Silvia Lucherini ,  Bruno Vajana

IPC分类号： H01L21/8247 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C17/12

CPC分类号： H01L27/11253 ,  H01L27/112 ,  H01L27/1126 ,  H01L27/11266

摘要： A ROM cell array in which the drains are more lightly doped than the sources. This reduces the worst-case capacitance seen by the bitlines, and consequently reduces the access time of the memory.

摘要翻译： 一个ROM单元阵列，其中漏极比源轻掺杂。 这减少了位线所看到的最坏情况电容，从而减少了存储器的访问时间。

公开(公告)号：US06548857B2

公开(公告)日：2003-04-15

申请号：US10052980

申请日：2002-01-17

申请人： Giovanna Dalla Libera ,  Bruno Vajana

发明人： Giovanna Dalla Libera ,  Bruno Vajana

IPC分类号： H01L2972

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor memory device having at least one memory cell row, each memory cell having an information storing element and a related select transistor for selecting the storing element. The select transistor includes a gate oxide region over a silicon substrate, a lower polysilicon layer and an upper polysilicon layer superimposed to the gate oxide region and electrically insulated by an intermediate dielectric layer interposed therebetween. The gate oxide regions of the select transistors of the at least one row are separated by field oxide regions, and the lower and upper polysilicon layers and the intermediate dielectric layer extend along the row over the gate oxide regions of the select transistors and over the field oxide regions. Along the row there is at least one opening in the upper polysilicon layer, intermediate dielectric layer and lower polysilicon layer, inside of which a first contact element suitable to electrically connect the lower and upper polysilicon layers is inserted.