Invention Grant
- Patent Title: Semiconductor memory device having faulty cells
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Application No.: US09886133Application Date: 2001-06-22
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Publication No.: US06388920B2Publication Date: 2002-05-14
- Inventor: Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
- Applicant: Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
- Priority: JP8-042451 19960229
- Main IPC: G11C1606
- IPC: G11C1606

Abstract:
In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
Public/Granted literature
- US20010036114A1 Semiconductor memory device having faulty cells Public/Granted day:2001-11-01
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