发明授权
- 专利标题: Vertical structure for semiconductor wafer-level chip scale packages
- 专利标题(中): 半导体晶圆级芯片级封装的垂直结构
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申请号: US09545287申请日: 2000-04-07
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公开(公告)号: US06392290B1公开(公告)日: 2002-05-21
- 发明人: Y. Mohammed Kasem , Yueh-Se Ho , Lee Shawn Luo , Chang-Sheng Chen , Eddy Tjhia , Bosco Lan , Jacek Korec , Anup Bhalla
- 申请人: Y. Mohammed Kasem , Yueh-Se Ho , Lee Shawn Luo , Chang-Sheng Chen , Eddy Tjhia , Bosco Lan , Jacek Korec , Anup Bhalla
- 主分类号: H01L2302
- IPC分类号: H01L2302
摘要:
In a semiconductor package for a chip having terminals on both sides, for example, a power MOSFET in which the gate and source terminals are on the front side and the drain terminal is on the back side, electrical contact is made with the back side terminal by extending vias, which can take the form of trenches, holes or other cavities, either entirely or patrially through the chip. The vias are filled with a metal or other electrically conductive material. The process is performed on the chips in a wafer simultaneously. The resulting package is compact and economical to manufacture and can readily be mounted, flip-chip style, on a printed circuit board.
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