公开(公告)号：US06833611B2

公开(公告)日：2004-12-21

申请号：US10445028

申请日：2003-05-27

Applicant: Sheng Tsung Liu ,  Francisco C. Cruz, Jr.

Inventor： Sheng Tsung Liu ,  Francisco C. Cruz, Jr.

IPC: H01L2302

CPC classification number: H01L24/85 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48195 ,  H01L2224/48233 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K2201/1053 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device mainly comprises a chip disposed on the upper surface of a substrate. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces arranged at the periphery of the ground ring and the power ring. The semiconductor device comprises at least a surface-mountable device connected across the ground ring and the power ring. The semiconductor device of the present invention is characterized by having at least a bonding wire formed across the surface-mountable device. The bonding wire is connected between one of the bonding pads of the chip and the power ring wherein at least one downward depression is formed in a lengthen portion at a top of the bonding wire.

Abstract translation: 半导体器件主要包括设置在基板的上表面上的芯片。 基板的上表面设置有接地环，功率环和布置在接地环和电源环周边的多个导电迹线。 半导体器件至少包括连接在接地环和电源环上的可表面安装的器件。 本发明的半导体器件的特征在于至少具有形成在表面安装装置上的接合线。 接合线连接在芯片的接合焊盘之一和动力环之间，其中至少一个向下的凹陷形成在接合线的顶部的延长部分中。

公开(公告)号：US06818977B2

公开(公告)日：2004-11-16

申请号：US10197986

申请日：2002-07-17

Applicant: Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L2302

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。

公开(公告)号：US06812556B2

公开(公告)日：2004-11-02

申请号：US10392934

申请日：2003-03-21

Applicant: Yasufumi Uchida

Inventor： Yasufumi Uchida

IPC: H01L2302

CPC classification number: H01L23/49531 ,  H01L23/49575 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10162 ,  H01L2924/15192 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A semiconductor device including a package body, a substrate contained within the package body and having a first side and an opposite second side, a first chip mounted on the first side of the substrate and within the package body, a second chip mounted on the second side of the substrate and within the package body and a plurality of leads each including an inner lead portion contained within the package body and an outer lead portion located outside the package body wherein each inner lead portion includes first and second bends to define a step configuration and wherein a distal end of each inner lead portion is mounted to the second side of the substrate.

Abstract translation: 一种半导体器件，包括封装主体，包含在封装主体内并具有第一侧和相对的第二侧的基板，安装在基板的第一侧上且在封装主体内的第一芯片，安装在第二侧上的第二芯片 并且包括多个引线，每个引线包括容纳在封装主体内的内引线部分和位于封装主体外部的外引线部分，其中每个内引线部分包括第一和第二弯曲部以限定步骤配置 并且其中每个内引线部分的远端安装到所述基板的第二侧。

公开(公告)号：US06798055B2

公开(公告)日：2004-09-28

申请号：US10175291

申请日：2002-06-20

Applicant: Venkateshwaran Vaiyapuri

Inventor： Venkateshwaran Vaiyapuri

IPC: H01L2302

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: Disclosed is a method of forming a support structure for supporting multiple dice and resulting structure. The support structure has a cavity with an upper die support surface, sidewalls providing the upper die support surface, and a lower die support bottom surface connected with the sidewalls. The support structure can be formed of a plurality of layers. A first semiconductor die is secured on the lower die support surface and a second semiconductor die is secured to the upper die support surface. An aperture can be formed from the structure bottom surface to the cavity to facilitate electrical connections between the first die and electrical contact areas on the support structure. An encapsulating material is formed around the dice, the electrical connections, and the vacant cavity space to form a packaged semiconductor device.

Abstract translation: 公开了一种形成用于支撑多个骰子和所得结构的支撑结构的方法。 支撑结构具有带有上模支撑表面的空腔，提供上模支撑表面的侧壁和与侧壁连接的下模支撑底表面。 支撑结构可以由多个层形成。 第一半导体管芯固定在下模支承表面上，第二半导体管芯固定在上模支承表面上。 可以从结构底表面到腔体形成孔，以便于第一管芯和支撑结构上的电接触区域之间的电连接。 围绕骰子，电连接和空腔空间形成封装材料以形成封装的半导体器件。

公开(公告)号：US06798050B1

公开(公告)日：2004-09-28

申请号：US09672783

申请日：2000-09-18

Applicant: Soichi Homma ,  Masahiro Miyata ,  Hirokazu Ezawa

Inventor： Soichi Homma ,  Masahiro Miyata ,  Hirokazu Ezawa

IPC: H01L2302

CPC classification number: H01L24/13 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/0496 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: After a copper diffusion preventing film 4 is formed on a copper pad 1, a barrier metal including a titanium film 5, a nickel film 6, and a palladium film 7 is formed on the copper diffusion preventing film 4. The copper diffusion preventing film formed on the copper pad suppresses diffusion of copper. Even when a solder bump is formed on the copper pad, diffusion of tin in the solder and copper is suppressed. This prevents formation of an intermetallic compound between copper and tin, so no interface de-adhesion or delamination occurs and a highly reliable connection is obtained. This structure can be realized by a simple fabrication process unlike a method of forming a thick barrier metal by electroplating. In this invention, high shear strength can be ensured by connecting a solder bump, gold wire, or gold bump to a copper pad without increasing the number of fabrication steps.

Abstract translation: 在铜焊盘1上形成铜扩散防止膜4之后，在铜扩散防止膜4上形成包含钛膜5，镍膜6和钯膜7的阻挡金属。形成铜扩散防止膜 在铜垫上抑制铜的扩散。 即使在铜焊盘上形成焊料凸块，也抑制锡在焊料和铜中的扩散。 这样可防止在铜和锡之间形成金属间化合物，因此不会发生界面剥离或脱层，并且获得高度可靠的连接。 这种结构可以通过简单的制造工艺来实现，这与通过电镀形成厚的阻挡金属的方法不同。 在本发明中，通过将焊锡凸块，金线或金凸块连接到铜焊盘上，可以确保高剪切强度，而不增加制造步骤的数量。

公开(公告)号：US06798049B1

公开(公告)日：2004-09-28

申请号：US09648284

申请日：2000-08-24

Applicant: Won Sun Shin ,  Do Sung Chun ,  Seon Goo Lee ,  Il Kwon Shim ,  Vincent DiCaprio

Inventor： Won Sun Shin ,  Do Sung Chun ,  Seon Goo Lee ,  Il Kwon Shim ,  Vincent DiCaprio

IPC: H01L2302

CPC classification number: H01L24/97 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A semiconductor package and method for fabricating the same is disclosed. In one embodiment, the semiconductor package includes a circuit board, at least two semiconductor chips, electric connection means, an encapsulant, and a plurality of conductive balls. The circuit board has a resin layer and a circuit pattern. The resin layer is provided with an opening at its center portion. The circuit pattern is formed on at least one of upper and lower surfaces of the resin layer and includes one or more bond fingers and ball lands exposed to the outside. The semiconductor chips have a plurality of input/output pads on an active surface thereof. The semiconductor chips are stacked at a position of the opening of the circuit board, with at least one of the chips being within the opening. Alternatively, both chips are in the opening. The electric connection means connects the input/output pads of the semiconductor chips to the bond fingers of the circuit board. The encapsulant surrounds the semiconductor chips so as to protect the chips from the external environment. The conductive balls are fusion-bonded on the ball lands of the circuit board.

Abstract translation: 公开了半导体封装及其制造方法。 在一个实施例中，半导体封装包括电路板，至少两个半导体芯片，电连接装置，密封剂和多个导电球。 电路板具有树脂层和电路图案。 树脂层在其中心部分设置有开口。 电路图案形成在树脂层的上表面和下表面中的至少一个上，并且包括暴露于外部的一个或多个粘合指状物和球状区域。 半导体芯片在其有效表面上具有多个输入/输出焊盘。 半导体芯片堆叠在电路板的开口的位置，其中至少一个芯片在开口内。 或者，两个芯片都在开口中。 电连接装置将半导体芯片的输入/输出焊盘连接到电路板的键合指状物。 密封剂围绕半导体芯片，以保护芯片免受外部环境的影响。 导电球熔接在电路板的球面上。

公开(公告)号：US06787890B2

公开(公告)日：2004-09-07

申请号：US10198976

申请日：2002-07-18

Applicant: Nan Tsung Huang ,  Chung Shin Mou

Inventor： Nan Tsung Huang ,  Chung Shin Mou

IPC: H01L2302

CPC classification number: H01S5/02276 ,  H01L2224/48091 ,  H01S5/4025 ,  H01L2924/00014

Abstract: An optical package structure (2) includes a cover (21) with a lens part (22), and a base member (23) which combines with the cover to define a closed space in which to package optical components. The base member has a bottom panel (232) and a substrate (234). A plurality of solder pads (231, 237) is provided on a top and bottom surfaces (2321, 2342) of the bottom panel and of the substrate. The solder pads on the top surface electrically connect with the optical components. A plurality of inner conductive traces (236, 238) is provided through the bottom panel and the substrate which electrically connect the solder pads on the top surface of the bottom panel with corresponding solder pads on the bottom surface of the substrate via printed circuits (235) on the substrate. Thus, an external electrical connection of the optical components is attained without wires and electrical pins.

Abstract translation: 光学封装结构（2）包括具有透镜部分（22）的盖子（21）和与盖子组合以限定封闭空间的基底构件（23），其中封装光学部件。 底座部件具有底板（232）和基板（234）。 多个焊盘（231,237）设置在底板和基板的顶表面和底表面（2321,2342）上。 顶表面上的焊盘与光学元件电连接。 多个内部导电迹线（236,238）设置穿过底部面板和基板，其通过印刷电路（235）将底部面板顶表面上的焊盘与相应的焊盘焊接在基底的底部表面上 ）。 因此，在没有电线和电引脚的情况下获得光学部件的外部电连接。

公开(公告)号：US06784529B2

公开(公告)日：2004-08-31

申请号：US10329342

申请日：2002-12-27

Applicant: Tatsuya Fukuda ,  Tomokazu Otani

Inventor： Tatsuya Fukuda ,  Tomokazu Otani

IPC: H01L2302

CPC classification number: H05K1/181 ,  H01L25/105 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A semiconductor device of the present invention includes the multi-stacked structure having the bottom semiconductor package with BGA or PGA terminals so that the total number of terminals of the semiconductor device can be increased without increasing the mounting area. In particular, the semiconductor device includes a first semiconductor package having an upper and lower surfaces. The first semiconductor package has a plurality of land terminals on the lower surface. The semiconductor device also includes a second semiconductor package having a planar configuration substantially the same as that of the first semiconductor package, which is provided on the upper surface of the first semiconductor package. The second semiconductor package has a plurality of lead terminals extending from a side surface of the second semiconductor package.

Abstract translation: 本发明的半导体器件包括具有BGA或PGA端子的底部半导体封装的多层结构，从而可以在不增加安装面积的情况下增加半导体器件的端子总数。 特别地，半导体器件包括具有上表面和下表面的第一半导体封装。 第一半导体封装在下表面上具有多个焊盘端子。 半导体器件还包括第二半导体封装，其具有与设置在第一半导体封装的上表面上的与第一半导体封装基本相同的平面配置。 第二半导体封装具有从第二半导体封装的侧表面延伸的多个引线端子。

公开(公告)号：US06781224B2

公开(公告)日：2004-08-24

申请号：US10262074

申请日：2002-10-02

Applicant: Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

Inventor： Yoshiyuki Yoneda ,  Masaharu Minamizawa ,  Eiji Watanabe ,  Mitsutaka Sato

IPC: H01L2302

CPC classification number: H01L21/6835 ,  H01L21/4846 ,  H01L21/563 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/49822 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor device substrate has fine terminals with a small pitch and is able to be easily produced at a low cost without using a special process. A mounting terminal has a pyramidal shape and extending between a front surface and a back surface of a silicon substrate. An end of the mounting terminal protrudes from the back surface of the silicon substrate. A wiring layer is formed on the front surface of the silicon substrate. The wiring layer includes a conductive layer that is electrically connected to the mounting terminal.

Abstract translation: 半导体器件基板具有细小的间距的端子，并且能够在不使用特殊工艺的情况下以低成本容易地制造。 安装端子具有金字塔形状并且在硅衬底的前表面和后表面之间延伸。 安装端子的一端从硅衬底的背面突出。 在硅衬底的前表面上形成布线层。 布线层包括电连接到安装端子的导电层。

公开(公告)号：US06781057B2

公开(公告)日：2004-08-24

申请号：US10722311

申请日：2003-11-25

Applicant: Daniel Reznik

Inventor： Daniel Reznik

IPC: H01L2302

CPC classification number: H01L23/045 ,  H01L23/49811 ,  H01L23/66 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/4823 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/12042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01S5/02212 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The invention relates to an electrical arrangement having a mount device with at least one conductor track, having an electrical component that is mounted on the mount device and is electrically connected to the at least one conductor track. The arrangement further includes a housing base plate on which the mount device is mounted and through which at least one contact-making pin extends, with the at least one contact-making pin being electrically connected to the at least one conductor track. In order to improve the frequency response of the arrangement, the invention provides for the at least one contact-making pin to touch the mount device and, in the area of the touching point, for a connection without any bonding wire to be provided between the at least one contact-making pin and the at least one conductor track on the mount device.

Abstract translation: 本发明涉及具有至少一个导体轨道的安装装置的电气装置，其具有安装在安装装置上并电连接至该至少一个导体轨道的电气部件。 该装置还包括壳体基板，安装装置安装在壳体基板上，并且至少一个接触引脚延伸穿过该壳体基座板，该至少一个接触引脚与至少一个导体轨道电连接。 为了提高布置的频率响应，本发明提供了至少一个接触引脚以接触安装装置，并且在接触点的区域中提供连接，而不需要在 至少一个接触制造销和该安装装置上的至少一个导体轨道。