A semiconductor memory device in which a memory cell array is divided into a plurality of operation blocks and one regular word line is activated simultaneously in each of two or more operation block. In the semiconductor memory device, when a defective regular word line is set for replacement with a spare word line, data is recorded in fuse ROM (read only memory) in the semiconductor memory device such that a regular word line to be replaced and a replacing spare word line are located in the same operation block or not located each in combined operation blocks which are activated simultaneously. This can prevent the simultaneous activation of a regular word line and a spare word line in the same operation block and malfunction of the semiconductor memory device.