发明授权
US06403388B1 Nanomachining method for integrated circuits 失效
集成电路的纳米加工方法

Nanomachining method for integrated circuits
摘要:
A system and method provides for effective analysis of an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, the system includes a system (e.g., a nanomachining arrangement) adapted to remove a selected portion of the backside of a semiconductor device having SOI structure, and to electrically isolate a selected portion of circuitry on the SOI semiconductor device circuitry side. The isolated circuitry then is analyzed.
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