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    Semiconductor die analysis via fiber optic communication
    1.
    发明授权
    Semiconductor die analysis via fiber optic communication 失效
    通过光纤通信进行半导体芯片分析

    公开(公告)号：US06850081B1

    公开(公告)日：2005-02-01

    申请号：US10164506

    申请日：2002-06-05

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： G01R31/28 ,  G01R31/319 ,  G01R31/303

    CPC分类号： G01R31/2884 ,  G01R31/31905

    摘要： Semiconductor analysis is improved via the use of fiber optic communications. According to an example embodiment of the present invention, a stimulation device is adapted to stimulate an integrated circuit die, and the die generates a response to the stimulation. An optical signal generator, either incorporated into the die or coupled to the die, detects the response, converts the response to an optical signal and transmits the optical signal. The optical signal is received at a testing arrangement adapted to analyze the die therefrom. The optical signal is used to analyze the die, improving signal quality and the ability to perform high-speed analysis of the die.

    摘要翻译： 通过使用光纤通信改进了半导体分析。 根据本发明的示例性实施例，刺激装置适于刺激集成电路管芯，并且管芯产生对刺激的响应。 将光信号发生器并入芯片或耦合到管芯，检测响应，将响应转换为光信号并发送光信号。 光学信号在适于从其分析模具的测试装置处被接收。 光信号用于分析芯片，提高信号质量和对芯片进行高速分析的能力。

    Defect detection in semiconductor devices
    2.
    发明授权
    Defect detection in semiconductor devices 失效
    半导体器件缺陷检测

    公开(公告)号：US06686757B1

    公开(公告)日：2004-02-03

    申请号：US09409217

    申请日：1999-09-30

    申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

    IPC分类号： G01R3128

    CPC分类号： G01R31/311

    摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

    摘要翻译： 根据本发明的示例性实施例，缺陷检测方法包括检测作为至少一个应用能量源的函数的集成电路中的缺陷的存在。 响应于施加到集成电路的能量，检测响应信号。 为参考集成电路器件开发包括振幅，频率，相位或频谱等信息的参数，然后与检测到的响应信号进行比较。 响应和参考信号的偏差以及所使用的能量源的类型与设备中的特定缺陷相关。

    Quadrant avalanche photodiode time-resolved detection
    3.
    发明授权
    Quadrant avalanche photodiode time-resolved detection 失效
    象限雪崩光电二极管时间分辨检测

    公开(公告)号：US06483327B1

    公开(公告)日：2002-11-19

    申请号：US09409088

    申请日：1999-09-30

    申请人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    发明人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

    IPC分类号： G01R31302

    CPC分类号： G01R1/071 ,  G01R31/311

    摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

    摘要翻译： 一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

    Acoustic 3D analysis of circuit structures
    4.
    发明授权
    Acoustic 3D analysis of circuit structures 失效
    电路结构的声学3D分析

    公开(公告)号：US06430728B1

    公开(公告)日：2002-08-06

    申请号：US09410147

    申请日：1999-09-30

    申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

    IPC分类号： G06F1750

    CPC分类号： G01R31/307 ,  G10K15/046

    摘要： According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.

    摘要翻译： 根据示例性实施例，本发明涉及用于分析集成电路的系统和方法。 激光被引导到集成电路的背面，并引起局部加热，其在电路中产生声能。 通过至少两个检测器检测集成电路中的声能传播。 使用来自检测器的检测到的声能，检测和定位至少一个电路缺陷。

    Selective state change analysis of a SOI die
    6.
    发明授权
    Selective state change analysis of a SOI die 失效
    SOI裸片的选择状态变化分析

    公开(公告)号：US06414335B1

    公开(公告)日：2002-07-02

    申请号：US09864688

    申请日：2001-05-23

    申请人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    发明人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

    IPC分类号： H01L2358

    CPC分类号： G01R31/312 ,  G01R31/307

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.

    摘要翻译： 通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。 状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。 强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

    Atomic force microscopy and signal acquisition via buried insulator
    7.
    发明授权
    Atomic force microscopy and signal acquisition via buried insulator 失效
    原子力显微镜和通过埋层绝缘子的信号采集

    公开(公告)号：US06448096B1

    公开(公告)日：2002-09-10

    申请号：US09864656

    申请日：2001-05-23

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： H01L2100

    CPC分类号： G01Q60/30 ,  G01R31/303 ,  Y10S977/854

    摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching the insulator layer of the SOI structure. According to an example embodiment of the present invention, a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side is analyzed. An atomic force microscope is scanned across a thinned portion of the back side. The microscope responds to an electrical characteristic, such as a logic state, coupled from circuitry via the insulator portion of the die over which the microscope is being scanned. The response of the microscope to the die is detected and used to detect an electrical characteristic of the die.

    摘要翻译： 通过从背面访问管芯内的电路而不必破坏SOI结构的绝缘体层来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，分析了具有SOI结构的半导体管芯和电路侧的背面相反的电路。 原子力显微镜扫描在背面的薄部分。 显微镜响应诸如逻辑状态的电特性，该电特性通过显微镜正被扫描的裸片的绝缘体部分从电路耦合。 检测显微镜对管芯的响应，并用于检测管芯的电气特性。

    Circuit access and analysis for a SOI flip-chip die
    8.
    发明授权
    Circuit access and analysis for a SOI flip-chip die 失效
    SOI倒装芯片的电路访问和分析

    公开(公告)号：US06448095B1

    公开(公告)日：2002-09-10

    申请号：US09755013

    申请日：2001-01-05

    申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

    IPC分类号： H01L2100

    CPC分类号： H01L22/20 ,  G01R31/307

    摘要： Analysis of a flip-chip type IC die having SOI structure is enhanced via analysis and repair of the die that make possible analysis that would typically result in the die being in a state of disrepair. According to an example embodiment of the present invention, a focused ion beam (FIB) is directed at a back side of a flip-chip die having a circuitry in a circuit side opposite a back side, wherein the circuitry including silicon on insulator (SOI) structure. The FIB is used to remove a selected portion of substrate including a portion of the insulator of the SOI structure from the die. The removed substrate exposes an insulator region in the die, and a signal is coupled from circuitry in the die via the exposed insulator region and used to analyze the die. Material is deposited in the exposed region and the selected portion of the die that had been removed is reconstructed. The reconstruction takes place before, during or after the signal is coupled, depending upon the die being analyzed and the type of analysis being performed. In this manner, access for analyzing the die is improved via the ability to couple a signal through the insulator and to repair a portion of the die that has been altered for analysis. Analysis that would otherwise be destructive can be performed and the ability of the die to function after analysis can be maintained.

    摘要翻译： 具有SOI结构的倒装芯片型IC芯片的分析通过分析和修复模具得到增强，这使得可能的分析通常导致模具处于失修状态。 根据本发明的一个示例性实施例，聚焦离子束（FIB）指向倒装芯片的背面，该倒装芯片的背面具有电路侧的电路，其中包括绝缘体上的硅（SOI） ） 结构体。 FIB用于从芯片去除包括SOI结构的绝缘体的一部分的衬底的选定部分。 去除的衬底暴露了管芯中的绝缘体区域，并且信号通过暴露的绝缘体区域从管芯中的电路耦合并用于分析管芯。 材料沉积在暴露的区域中，并且已经去除的模具的选定部分被重建。 重建在信号耦合之前，期间或之后进行，这取决于正在分析的管芯和正在执行的分析的类型。 以这种方式，通过能够通过绝缘体耦合信号并修复已经被改变以用于分析的芯片的一部分的能力来提高用于分析芯片的访问。 否则可以进行破坏性的分析，可以保持分析后的模具功能的能力。

    Selective back side reactive ion etch
    9.
    发明授权
    Selective back side reactive ion etch 失效
    选择性背面反应离子蚀刻

    公开(公告)号：US06355564B1

    公开(公告)日：2002-03-12

    申请号：US09384080

    申请日：1999-08-26

    申请人： Jeffrey D. Birdsley ,  Matthew Thayer

    发明人： Jeffrey D. Birdsley ,  Matthew Thayer

    IPC分类号： H01L2166

    CPC分类号： G01R31/311 ,  G01N1/32 ,  H01L21/3065

    摘要： According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. An ion gas comprising SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region in the back side is selectively etched using reactive ion etching (RIE) and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.

    摘要翻译： 根据示例性实施例，分析了具有背侧和与背面相反的电路侧的半导体器件。 半导体器件包括背面的体硅，并且还包括外延硅。 包含SF 6和N 2的离子气体指向后侧的目标区域。 使用离子气体，使用反应离子蚀刻（RIE）来选择性地蚀刻后侧的目标区域，并且形成暴露区域。 蚀刻对体硅有选择性。 当蚀刻工艺遇到外延硅时，蚀刻速率减慢并被用作选择性蚀刻工艺的端点指示器。 一旦蚀刻过程停止，电路就通过暴露的区域被访问。