发明授权
US06404236B1 Domino logic circuit having multiplicity of gate dielectric thicknesses
有权
具有多个栅介质厚度的多米诺逻辑电路
- 专利标题: Domino logic circuit having multiplicity of gate dielectric thicknesses
- 专利标题(中): 具有多个栅介质厚度的多米诺逻辑电路
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申请号: US09811967申请日: 2001-03-19
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公开(公告)号: US06404236B1公开(公告)日: 2002-06-11
- 发明人: Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
- 申请人: Kerry Bernstein , Andres Bryant , Robert J. Gauthier, Jr. , Edward Joseph Nowak , Minh Ho Tong
- 主分类号: H03K19096
- IPC分类号: H03K19096
摘要:
A domino logic circuit having a clocked precharge is disclosed. The domino logic circuit includes a precharge transistor, an isolation transistor, and multiple evaluate transistors. Connected to a power supply, the precharge transistor receives a clock input. The isolation transistor is connected to ground and also receives the clock input. Each of the input transistors, which are coupled between the precharge transistor and the isolation transistor, receives a signal input. The gate dielectric thickness of the evaluate transistors is less than the gate dielectric thickness of the precharge transistor.
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