发明授权
US06404264B2 Fuse latch having multiplexers with reduced sizes and lower power consumption 有权
保险丝锁存器具有减小尺寸和较低功耗的多路复用器

  • 专利标题: Fuse latch having multiplexers with reduced sizes and lower power consumption
  • 专利标题(中): 保险丝锁存器具有减小尺寸和较低功耗的多路复用器
  • 申请号: US09455118
    申请日: 1999-12-06
  • 公开(公告)号: US06404264B2
    公开(公告)日: 2002-06-11
  • 发明人: Gabriel DanielToshiaki Kirihata
  • 申请人: Gabriel DanielToshiaki Kirihata
  • 主分类号: H03K1762
  • IPC分类号: H03K1762
Fuse latch having multiplexers with reduced sizes and lower power consumption
摘要:
A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.
信息查询
0/0