公开(公告)号：US06288436B1

公开(公告)日：2001-09-11

申请号：US09361960

申请日：1999-07-27

申请人： Chandrasekhar Narayan ,  Kenneth Arndt ,  Toshiaki Kirihata ,  David Lachtrupp ,  Axel Brintzinger ,  Gabriel Daniel

发明人： Chandrasekhar Narayan ,  Kenneth Arndt ,  Toshiaki Kirihata ,  David Lachtrupp ,  Axel Brintzinger ,  Gabriel Daniel

IPC分类号： H01L2900

CPC分类号： H01L22/22 ,  H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

摘要翻译： 多种不同类型的保险丝，每种类型的用于特定用途的保险丝都位于半导体集成电路晶片上，其中激活一种类型的保险丝不会使不同类型的保险丝失效。 第一种类型的保险丝，例如激光激活的保险丝，主要用于修复晶圆级的缺陷，而第二种类型的保险丝，例如电激活保险丝，用于修复将IC芯片安装在模块上所发现的缺陷 并在老化测试中强调模块。 模块级别的缺陷通常是单电池故障，它们由电气编程的保险丝固化，以激活模块级冗余。

公开(公告)号：US6166981A

公开(公告)日：2000-12-26

申请号：US512922

申请日：2000-02-25

申请人： Toshiaki Kirihata ,  Gabriel Daniel

发明人： Toshiaki Kirihata ,  Gabriel Daniel

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/802

摘要： A memory device that includes a plurality of data storage cells; at least one redundancy data storage cell; a redundancy match detection circuit; and a means for coupling programmable fuses to the redundancy match detection circuit, wherein a defective data storage is replaced by one redundancy data storage when the redundancy match detection detects a pre-determined condition set by said programmable fuse is described. Decoding is accomplished by a data bus selecting the e-fuse to be blown. The data bus is also used for reading the state of the e-fuses to ensure that the e-fuses are correctly blown. Power is effectively applied to the selected e-fuses while sharing the data bus for e-fuse decoding and verification. In order to reduce the number of communication channels between e-fuses and the redundancy match detection circuitry, the transfer operation uses time multiplexing, allowing e-fuse information to be transferred to the redundancy match detection circuitry sequentially. The actual time multiplexing operation for performing the transfer is preferably enabled only after the chip power-up state.

摘要翻译： 一种包括多个数据存储单元的存储器件; 至少一个冗余数据存储单元; 冗余匹配检测电路; 以及用于将可编程保险丝耦合到冗余匹配检测电路的装置，其中描述了当冗余匹配检测检测到由所述可编程熔丝设置的预定条件时，由一个冗余数据存储器替换有缺陷的数据存储器。 通过选择要熔断的电熔丝的数据总线实现解码。 数据总线还用于读取电子保险丝的状态，以确保电子保险丝正确吹扫。 电源有效地应用于选定的电子保险丝，同时共享用于电子熔丝解码和验证的数据总线。 为了减少电子熔断器与冗余匹配检测电路之间的通信信道的数量，传输操作使用时间复用，允许电子熔丝信息被顺序传送到冗余匹配检测电路。 用于执行传送的实际时间多路复用操作优选仅在芯片上电状态之后才能使能。

公开(公告)号：US06404264B2

公开(公告)日：2002-06-11

申请号：US09455118

申请日：1999-12-06

申请人： Gabriel Daniel ,  Toshiaki Kirihata

发明人： Gabriel Daniel ,  Toshiaki Kirihata

IPC分类号： H03K1762

CPC分类号： G11C29/83 ,  G11C8/08 ,  G11C17/18

摘要： A fuse latch for a memory circuit according to the present invention comprises a plurality of address lines, a control signal line provided from a fuse, a multiplexer for multiplexing the plurality of address lines in response to the control signal wherein the multiplexer has only one type transistors, and a decoder for receiving a multiplexed signal from the multiplexer. Since the multiplexer has a smaller size than that of a conventional CMOS multiplexer, a fuse latch circuit of the present invention has a smaller size than that of a conventional fuse latch. The multiplexer preferably has only NMOS transistors. To overcome a voltage drop due to an NMOS threshold voltage, the present invention uses low-threshold NMOSs and/or boosts the transistors in the multiplexer. Alternatively, the voltage drop is successfully converted into a CMOS level by using a dynamic logic circuit. Further, current consumption of a fuse latch circuit of the present invention is reduced by adopting NMOS transistors to which a lower voltage level may be applied.

摘要翻译： 根据本发明的用于存储器电路的熔丝锁存器包括多个地址线，从熔丝提供的控制信号线，多路复用器，用于响应于控制信号多路复用多个地址线，其中多路复用器仅具有一种类型 晶体管和用于从多路复用器接收多路复用信号的解码器。 由于多路复用器具有比常规CMOS多路复用器更小的尺寸，因此本发明的熔丝锁存电路具有比常规熔丝锁存器更小的尺寸。 多路复用器优选地仅具有NMOS晶体管。 为了克服由于NMOS阈值电压引起的电压降，本发明使用低阈值NMOS和/或升压多路复用器中的晶体管。 或者，通过使用动态逻辑电路将电压降成功地转换成CMOS电平。 此外，通过采用可施加较低电压电平的NMOS晶体管来减少本发明的熔丝锁存电路的电流消耗。

公开(公告)号：US6052318A

公开(公告)日：2000-04-18

申请号：US218561

申请日：1998-12-22

申请人： Toshiaki Kirihata ,  Gabriel Daniel

发明人： Toshiaki Kirihata ,  Gabriel Daniel

IPC分类号： G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/816 ,  G11C11/401

摘要： The present disclosure relates to semiconductor memories and more particularly, to an improved method and apparatus for replacing defective row/column lines. In accordance with the present invention, a high replacement flexibility redundancy and method is employed to increase chip yield and prevent sense amplifier signal contention. Redundancy elements are integrated in at least two of a plurality of memory arrays, which don't share the sense amplifiers. Thus, no additional sense amplifiers are required. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block, which does not share sense amplifiers with the first block. The corresponding row/column is replaced to mimic the redundancy replacement of the first block thereby increasing flexibility and yield as well as preventing sensing signal contention.

摘要翻译： 本公开涉及半导体存储器，更具体地，涉及用于替换有缺陷的行/列线的改进的方法和装置。 根据本发明，采用高替换灵活性冗余和方法来提高芯片产量并防止感测放大器信号争用。 冗余元件集成在不共享读出放大器的多个存储器阵列中的至少两个中。 因此，不需要额外的感测放大器。 第一个阵列或块中的有缺陷的行/列线被自己的冗余中的冗余行/列线代替。 无论是否有故障，相应的行/列线被替换为不与第一块共享读出放大器的第二阵列或块。 相应的行/列被替换以模拟第一块的冗余替换，从而增加灵活性和产量以及防止感测信号争用。

公开(公告)号：US07087975B2

公开(公告)日：2006-08-08

申请号：US09751474

申请日：2000-12-28

申请人： Gunther Lehmann ,  Axel Christoph Brintzinger ,  Gabriel Daniel

发明人： Gunther Lehmann ,  Axel Christoph Brintzinger ,  Gabriel Daniel

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

摘要翻译： 提供一种半导体器件，其由具有在其表面上的垂直堆叠关系中的至少两个反熔丝的区域有效布置的晶片形成，并且在其间共享公共中间电极。 该装置包括至少一个下部反熔丝，其具有下部对电极和下部可熔绝缘体部分，该熔断绝缘体部分限定了将下部反电极与公共中间电极互连的初始高电阻状态的下部熔丝元件，以及至少一个上部反熔丝， 其可以与下部反熔丝相同或不同，上部反熔丝具有上部对电极和上部可熔绝缘体部分，其限定具有初始高电阻状态的上部熔丝元件，其将上部对置电极与公共中间电极 。

公开(公告)号：US06426911B1

公开(公告)日：2002-07-30

申请号：US09691953

申请日：2000-10-19

申请人： Gunther Lehmann ,  Gabriel Daniel ,  Gerd Frankowsky

发明人： Gunther Lehmann ,  Gabriel Daniel ,  Gerd Frankowsky

IPC分类号： G11C700

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A circuit for programming electrical fuses, in accordance with the present invention, includes a shift register including a plurality of latches. Each latch has a corresponding switch and a corresponding electrical fuse. A bit generator generates a single bit of a first state and all other bits of a second state. The bit generator propagates the generated bits into the shift register in accordance with a clock signal. Each switch enables conduction through the corresponding electrical fuse in accordance with the generated bits stored in the corresponding latch. A blow voltage line connects to the electrical fuses. The blow voltage line is activated to blow fuses in accordance with programming data such that the electrical fuses are programmed in accordance with the programming data when the single bit of the first state is stored in the latch corresponding to the fuse to be programmed.

摘要翻译： 根据本发明的用于编程电熔丝的电路包括一个包括多个锁存器的移位寄存器。 每个闩锁都有相应的开关和相应的电保险丝。 位发生器产生第一状态的单个位和第二状态的所有其他位。 位产生器根据时钟信号将生成的比特传播到移位寄存器。 每个开关根据存储在相应的锁存器中的产生的位使能通过相应的电熔丝的导通。 吹电压线路连接到电气保险丝。 根据编程数据激活吹制电压线，以便根据编程数据来熔断熔丝，使得当第一状态的单个位被存储在对应于要编程的熔丝的锁存器中时，根据编程数据编程电熔丝。

公开(公告)号：US06285619B1

公开(公告)日：2001-09-04

申请号：US09442982

申请日：1999-11-18

申请人： Gabriel Daniel ,  Oliver Weinfurtner

发明人： Gabriel Daniel ,  Oliver Weinfurtner

IPC分类号： G11C700

CPC分类号： G11C17/16 ,  G11C17/14

摘要： A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

摘要翻译： 提供了一种用于存储数据位的电路，其中电路包括具有第一端和第二端的第一保险丝和具有第三端和第四端的第二保险丝。 第一个保险丝的第一端连接到一个逻辑0输入，其第二端连接到一个公共输出端。 第二个保险丝的第三端连接到逻辑1输入，第四端连接到公共输出端。 为了存储数据位，选择性地吹制第一和第二熔丝之一。 因此，可以使用两个保险丝来存储一些信息。

公开(公告)号：US6008523A

公开(公告)日：1999-12-28

申请号：US140573

申请日：1998-08-26

申请人： Chandrasekhar Narayan ,  Axel Brintzinger ,  Gabriel Daniel ,  Fred Einspruch

发明人： Chandrasekhar Narayan ,  Axel Brintzinger ,  Gabriel Daniel ,  Fred Einspruch

IPC分类号： H01L21/82 ,  G11C29/04 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/00 ,  H01L27/108 ,  H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002

摘要： A semiconductor device includes an array of electrical fuses having a structure which permits tight fuse pitches while enabling electrical fusing at voltages of about 10 volts or less. The fuses are useful to replace defective components of the device and/or to permit custom wiring. The semiconductor device includes a substrate with a tight pitch array of fuses including a plurality of fuse links of selective cross sectional area in closely adjacent arrangement, each connected at one end to an individual connector terminal of larger cross sectional area than that of the fuse link, and at another end to a common connector terminal of larger cross sectional area than that of the individual connector terminals. The common connector terminal is typically held at a less positive potential than one of the individual connector terminals during the time a fuse link thereat is to be opened such that electron flow is in a direction from the common connector terminal to the fuse link. The common connector terminal cross sectional area is desirably about 2 or more times that of the individual fuse links to enable electrical fusing at voltages of about 10 volts or less.

摘要翻译： 半导体器件包括电熔丝阵列，其具有允许紧密的熔断器间距的结构，同时在约10伏或更小的电压下实现电熔断。 保险丝可用于更换设备的有缺陷的部件和/或允许定制接线。 半导体器件包括具有紧密间距阵列的保险丝的衬底，其包括紧密相邻布置的选择性横截面积的多个熔丝链，每个熔断体的一端连接到具有比熔丝链的横截面积大的截面面积的单个连接器端子 并且在另一端连接到具有比各个连接器端子更大横截面积的公共连接器端子。 通常，连接器端子通常保持在比其中一个单独的连接器端子更小的正电位，在其中的熔断体将被打开，使得电子流在从公共连接器端子到熔丝链的方向上。 共同的连接器端子横截面积理想的是大约是单个熔断体的2倍或更多倍，以使得能够在约10伏或更小的电压下进行电熔断。

公开(公告)号：US5929684A

公开(公告)日：1999-07-27

申请号：US036486

申请日：1998-03-06

申请人： Gabriel Daniel

发明人： Gabriel Daniel

IPC分类号： H03K5/04 ,  G06F1/04

CPC分类号： H03K5/04

摘要： Feedback pulse generators each have an input and an output, a first digital gating circuit, and a second digital gating circuit. The first digital gating circuit is coupled between the input and the output of the pulse generator, and is responsive to an input signal from an external source changing from a first logic state to a second logic state that is received at a first input thereof for initiating a pulse at the output of the pulse generator. The second digital gating circuit is coupled in a feedback path between the output of the pulse generator and a second input to the first digital gating circuit, the second digital gating circuit is responsive to the initiation of the pulse at the output of the pulse generator while the input signal from the external source is in the second logic state for providing a control signal with a predetermined delay to the first digital gating circuit for terminating the pulse at the output of the pulse generator so that the pulse is available for a predetermined period of time essentially independent of any load on the output of the pulse generator.

摘要翻译： 反馈脉冲发生器各自具有输入和输出，第一数字门控电路和第二数字门控电路。 第一数字选通电路耦合在脉冲发生器的输入和输出之间，并且响应于来自外部源的输入信号从第一逻辑状态改变到第二逻辑状态，该第二逻辑状态在其第一输入处被接收，用于启动 脉冲发生器输出端的脉冲。 第二数字选通电路被耦合在脉冲发生器的输出端与第一数字选通电路的第二输入端之间的反馈路径中，第二数字选通电路响应脉冲发生器的输出处的脉冲的启动， 来自外部源的输入信号处于第二逻辑状态，用于向第一数字选通电路提供具有预定延迟的控制信号，用于在脉冲发生器的输出处终止脉冲，使得脉冲可用于预定时间段 时间基本上与脉冲发生器输出上的任何负载无关。