A microprocessor configured to decode a plurality of instruction bytes in parallel is disclosed. The microprocessor may comprise a plurality of single-byte decoder/execution units that are configured to receive instruction bytes and cross-talk to determine instruction boundaries and instruction field boundaries. Once and instruction has been identified, a determination is made as to whether or not the instruction is a simple instruction. Simple instructions are executed within the decoder/execution units, while complex instructions are forwarded to full-fledged functional units. A computer system and method for predecoding instructions are also disclosed.