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1.发明授权
公开(公告)号：US6141740A
公开(公告)日：2000-10-31
申请号：US808483
申请日：1997-03-03
CPC分类号： G06F9/30185 , G06F8/66 , G06F9/268 , G06F9/30189 , G06F9/328 , G06F12/0875
摘要： A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of microcode in the microcode instruction unit. If the flag bit is asserted, the microcode instruction unit branches to a patch microcode routine that causes a substitute microcode instruction stored in external RAM to be loaded into patch data registers. The transfer of the substitute microcode instruction to the patch data registers is accomplished using data transfer procedures. The microcode instruction unit then dispatches the substitute instructions stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the existing microcode instruction.
摘要翻译： 超标量微处理器实现微代码指令单元，其用替代微代码指令对现有的微代码指令进行补丁。 标记位与微代码指令单元中的每一行微代码相关联。 如果标志位被置位，则微代码指令单元分支到补丁微代码程序，使得存储在外部RAM中的替代微代码指令被加载到补丁数据寄存器中。 使用数据传输程序来实现代替微码指令到补丁数据寄存器的传送。 然后微代码指令单元分派存储在补丁数据寄存器中的替代指令，代替指令由功能单元代替现有的微代码指令执行。
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公开(公告)号：US5933629A
公开(公告)日：1999-08-03
申请号：US873360
申请日：1997-06-12
CPC分类号： G06F9/3804 , G06F9/28 , G06F9/30152 , G06F9/3816 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： A superscalar microprocessor implements a microcode instruction unit with sequence control fields appended to each microcode line. The sequence control fields indicate whether a subsequent line contains a branch instruction, whether a subsequent line is the last line in a microcode sequence, and other sequence control information. The sequence control information is accessed one cycle before the microcode line. This allows the next address to be calculated in parallel with the accessing of the microcode instruction line. By generating the next address in parallel with accessing the microcode line, the time delay from accessing one microcode line to accessing the next microcode line is reduced. The sequence control field additionally indicates how many microcode instructions are in the last line of the microcode sequence. If the last microcode line of the microcode sequence contains less instructions than the number of issue positions available, fastpath, or directly decodable instructions, can be issued with the final microcode line.
摘要翻译： 超标量微处理器实现了附加到每个微码行的序列控制字段的微代码指令单元。 序列控制字段指示后续行是否包含分支指令，后续行是否是微代码序列中的最后一行，以及其他序列控制信息。 序列控制信息在微代码行之前一个周期访问。 这允许与微代码指令行的访问并行计算下一个地址。 通过与访问微代码行并行地生成下一个地址，减少了访问一个微代码行到访问下一个微代码行的时间延迟。 序列控制字段另外指示微代码序列的最后一行中有多少个微代码指令。 如果微代码序列的最后一个微代码行包含的指令数量少于可用的发布位置的数量，则可以使用最终的微代码行发出快速路径或直接可解码的指令。
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3.发明授权Microprocessor configured to simultaneously dispatch microcode and directly-decoded instructions 失效微处理器配置为同时调度微代码和直接解码的指令
公开(公告)号：US5867680A
公开(公告)日：1999-02-02
申请号：US685655
申请日：1996-07-24
CPC分类号： G06F9/382 , G06F9/3842 , G06F9/3844 , G06F9/3853
摘要： An instruction dispatch apparatus is provided in which a directly-decoded instruction and a microcode instruction are concurrently dispatched ("packed"). The instruction which is second in program order is retained until the succeeding clock cycle. During the succeeding clock cycle, a microcode unit determines if the microcode instruction and the directly-decoded instruction, when taken together, occupy less than or equal to the total number of issue positions available in the microprocessor. If the microcode unit determines that less than or equal to the total number of issue positions are occupied, then the packing is successful. If the microcode unit determines that greater than the total number of issue positions are occupied, then the packing is unsuccessful and the retained instruction is redispatched. Additionally, instruction dispatch selection is performed in two phases. First, a number of instructions are selected as potentially dispatchable instructions. From the potentially dispatchable instructions, a set of actually dispatched instructions may be selected based upon the success or failure of instruction packing during the previous clock cycle and whether or not packing was performed. If instruction packing was not performed during the previous clock cycle or was performed unsuccessfully, then the instructions which are foremost in program order within the potentially dispatchable instructions are selected. However, if instruction packing was successfully performed in the previous clock cycle, then the retained instruction is not selected for dispatch.
摘要翻译： 提供了一种指令调度装置，其中直接解码的指令和微代码指令被同时调度（“打包”）。 按程序顺序排列的第二个指令将保留到下一个时钟周期。 在随后的时钟周期期间，微代码单元确定微代码指令和直接解码的指令如果一起占用小于或等于微处理器中可用的发布位置的总数。 如果微码单元确定小于或等于所占用的发布位置的总数，则打包成功。 如果微代码单元确定大于占用的发布位置的总数，则打包不成功，并且保留的指令被重新分配。 此外，指令分派选择分两个阶段执行。 首先，选择许多指令作为潜在的可分派指令。 根据潜在可分派指令，可以基于在先前时钟周期期间的指令打包的成功或失败以及是否执行打包来选择一组实际分派的指令。 如果在上一个时钟周期内没有执行指令打包或执行失败，则可以选择潜在的可调度指令中以程序顺序排列的指令。 但是，如果在上一个时钟周期内成功执行指令打包，则不会选择保留的指令进行调度。
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公开(公告)号：US5491653A
公开(公告)日：1996-02-13
申请号：US318924
申请日：1994-10-06
申请人： Michael P. Taborn , Paul K. Miller
发明人： Michael P. Taborn , Paul K. Miller
CPC分类号： G06F7/5016
摘要： A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is connected to the output of a first precharge transistor that is powered by the upper rail and controlled by a clock. The output of a second transistor of the pair of cross-coupled transistors is connected to the output of a second precharge transistor that is powered by the upper rail and controlled by the clock. A logic circuit is wired to perform a logical function, either a Sum or a Carry function, and has a plurality of inputs, an output, and a complementary output. The output of the logic circuit is connected to the output of the first transistor of the pair of cross-coupled transistors, and the complementary output is connected to the output of the second transistor of the pair of cross-coupled transistors. An enable transistor having a first terminal connected to a lower voltage rail, and being controlled by the complement of the clock, has a second terminal connected to the logic circuit such that the logic circuit is connected to the lower voltage rail through the enable transistor.
摘要翻译： 提供具有差分信号响应和输出的进位保存加法器电路。 该电路包括由上电压轨供电的一对交叉耦合晶体管。 一对交叉耦合晶体管中的第一晶体管的输出连接到由上轨道供电并由时钟控制的第一预充电晶体管的输出。 一对交叉耦合晶体管中的第二晶体管的输出端与第二预充电晶体管的输出端连接，该第二预充电晶体管由上轨道供电并由时钟控制。 逻辑电路被布线以执行逻辑功能，即Sum或Carry功能，并且具有多个输入，输出和互补输出。 逻辑电路的输出端连接到一对交叉耦合晶体管的第一晶体管的输出端，互补输出端连接到一对交叉耦合晶体管的第二晶体管的输出端。 具有连接到较低电压轨的第一端子并由时钟的补码控制的使能晶体管具有连接到逻辑电路的第二端子，使得逻辑电路通过使能晶体管连接到较低电压轨。
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5.发明申请METHOD FOR MANIPULATING AND REPARTITIONING A HIERARCHICAL INTEGRATED CIRCUIT DESIGN 有权用于操纵和分级分层集成电路设计的方法公开(公告)号：US20120192132A1
公开(公告)日：2012-07-26
申请号：US13196005
申请日：2011-08-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.
摘要翻译： 可以获得包含一个或多个层次的原始电路块的硬件描述语言表示。 一些或全部层级可以被解散以在相同的层级下访问原始电路块内的每个电路组件。 然后将指定电路组件分组在一起以在新的层次结构上创建新的电路块。 每个新电路块内的组件和信号可以被重新命名以在逻辑上对应的组件和彼此之间的信号与新的电路块相匹配。 可以为每个新的电路块添加缺少的引脚，并且连接到新的电路块内的相应的相关联的信号，并且逻辑上等同的引脚可以被赋予相同的名称，以确保新的电路块在逻辑上彼此相等并具有相同的接口。 可以选择新的电路块之一用于物理构建以获得与所选择的新电路块相对应的一个或多个物理实例，并且顶层构建可以将每个新的电路块实例链接到那些一个或多个物理实例中的一个。
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6.发明授权公开(公告)号：US06405303B1
公开(公告)日：2002-06-11
申请号：US09388211
申请日：1999-08-31
IPC分类号： G06F938
CPC分类号： G06F9/3017 , G06F9/30149 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3867
摘要： A microprocessor configured to decode a plurality of instruction bytes in parallel is disclosed. The microprocessor may comprise a plurality of single-byte decoder/execution units that are configured to receive instruction bytes and cross-talk to determine instruction boundaries and instruction field boundaries. Once and instruction has been identified, a determination is made as to whether or not the instruction is a simple instruction. Simple instructions are executed within the decoder/execution units, while complex instructions are forwarded to full-fledged functional units. A computer system and method for predecoding instructions are also disclosed.
摘要翻译： 公开了一种被配置为并行地解码多个指令字节的微处理器。 微处理器可以包括被配置为接收指令字节和串扰以确定指令边界和指令字段边界的多个单字节解码器/执行单元。 一旦确定了指令，则确定指令是否是简单指令。 简单的指令在解码器/执行单元中执行，而复杂的指令被转发到完整的功能单元。 还公开了一种用于预解码指令的计算机系统和方法。
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7.发明授权Floating point and multimedia unit with data type reclassification capability 失效具有数据类型重新分类能力的浮点数和多媒体单元
公开(公告)号：US5978901A
公开(公告)日：1999-11-02
申请号：US916056
申请日：1997-08-21
申请人： Mark R. Luedtke , Paul K. Miller , Chris N. Hinds , Ashraf Ahmed
发明人： Mark R. Luedtke , Paul K. Miller , Chris N. Hinds , Ashraf Ahmed
CPC分类号： G06F9/3891 , G06F9/30105 , G06F9/30134 , G06F9/30192 , G06F9/3885
摘要： A superscalar microprocessor includes a combination floating point and multimedia unit. The floating point and multimedia unit includes one set of registers. The multimedia core and floating point core share the one set of registers. Each register as a type field associated with the register. The type field identifies whether the associated register contains valid data and whether the data is of multimedia type or floating point type. If the register stores floating point type data, the type field further indicates which of a plurality of floating point types the register stores such as: zero, infinity and normal. The floating point core relies on the type field to identify special floating point numbers such as zero and infinity. To ensure predictable results when a floating point instruction is executed subsequent to a multimedia instruction, a retyping algorithm retypes registers typed as multimedia type when the first floating point instruction subsequent to a multimedia instruction is executed. The retyping algorithm reads each register and reclassifies the registers classified as multimedia type. The reclassification algorithm classifies the contents of the register interpreted as floating point data.
摘要翻译： 超标量微处理器包括组合浮点和多媒体单元。 浮点和多媒体单元包括一组寄存器。 多媒体核心和浮点核心共享一组寄存器。 每个寄存器作为与寄存器相关联的类型字段。 类型字段标识相关联的寄存器是否包含有效数据以及数据是多媒体类型还是浮点型。 如果寄存器存储浮点型数据，则类型字段进一步指示寄存器存储的多个浮点类型中的哪一种，例如：零，无穷大和正常。 浮点核心依赖于类型字段来识别特殊浮点数，例如零和无穷大。 为了在多媒体指令之后执行浮点指令时确保可预测的结果，当执行多媒体指令之后的第一个浮点指令时，重新输入算法重新输入类型为多媒体类型的寄存器。 重新输入法算法读取每个寄存器并重新分类归类为多媒体类型的寄存器。 重分类算法将寄存器的内容分类为浮点数据。
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8.发明授权Method for manipulating and repartitioning a hierarchical integrated circuit design 有权用于操纵和重新分配分层集成电路设计的方法公开(公告)号：US08397190B2
公开(公告)日：2013-03-12
申请号：US13196005
申请日：2011-08-02
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A hardware description language representation of an original circuit block containing one or more hierarchies may be obtained. Some, or all of the hierarchies may be dissolved to access each circuit component within the original circuit block at a same level of hierarchy. Designated circuit components may then be grouped together to create new circuit blocks at a new level of hierarchy. Components and signals within each new circuit block may be renamed to match logically corresponding components and signals within each other new circuit block. Missing pins may be added for each new circuit block, and connected to respective associated signals within the new circuit block, and logically equivalent pins may be given the same name to ensure the new circuit blocks are logically equivalent to each other and have identical interfaces. One of the new circuit blocks may be selected for physical build to obtain one or more physical instances corresponding to the selected new circuit block, and a top-level build may link each new circuit block instance to one of those one or more physical instances.
摘要翻译： 可以获得包含一个或多个层次的原始电路块的硬件描述语言表示。 一些或全部层级可以被解散以在相同的层级下访问原始电路块内的每个电路组件。 然后将指定电路组件分组在一起以在新的层次结构上创建新的电路块。 每个新电路块内的组件和信号可以被重新命名以在逻辑上对应的组件和彼此之间的信号与新的电路块相匹配。 可以为每个新的电路块添加缺少的引脚，并且连接到新的电路块内的相应的相关联的信号，并且逻辑上等同的引脚可以被赋予相同的名称，以确保新的电路块在逻辑上彼此相等并具有相同的接口。 可以选择新的电路块之一用于物理构建以获得与所选择的新电路块相对应的一个或多个物理实例，并且顶层构建可以将每个新的电路块实例链接到那些一个或多个物理实例中的一个。
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公开(公告)号：US06460132B1
公开(公告)日：2002-10-01
申请号：US09387024
申请日：1999-08-31
申请人： Paul K. Miller
发明人： Paul K. Miller
IPC分类号： G06F1100
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F9/3861
摘要： A microprocessor configured to predecode variable length instructions in a massively parallel fashion is disclosed. The microprocessor may comprise a prefetch fetch unit configured to read instruction bytes from memory and a plurality of predecode unit configured to receive and predecode the instruction bytes. The predecode units are configured to operate separately and in parallel to generate one or more predecode bits per instruction byte. The microprocessor may further include a predecode bit correction unit configured to receive, verify, and correct the predecode bits from the parallel predecode units. A computer system and method for predecoding instructions are also disclosed.
摘要翻译： 公开了以大规模并行方式对可变长度指令进行预解码的微处理器。 微处理器可以包括被配置为从存储器读取指令字节的预取取取单元和被配置为接收和预解码指令字节的多个预解码单元。 预解码单元配置为单独并行并行运行以产生每个指令字节的一个或多个预解码位。 微处理器还可以包括预解码比特校正单元，其被配置为从并行预解码单元接收，验证和校正预解码比特。 还公开了一种用于预解码指令的计算机系统和方法。
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公开(公告)号：US06339822B1
公开(公告)日：2002-01-15
申请号：US09165609
申请日：1998-10-02
申请人： Paul K. Miller
发明人： Paul K. Miller
IPC分类号： G06F1500
CPC分类号： G06F9/3863 , G06F9/30149 , G06F9/3804 , G06F9/3806 , G06F9/3814 , G06F9/3816 , G06F9/382 , G06F9/3836 , G06F2212/6032
摘要： A microprocessor configured to cache basic blocks of instructions is disclosed. The microprocessor may comprise decoding logic, a basic block cache, and a branch prediction unit. The decoding logic is coupled to receive and decode variable-length instructions into padded instructions that have one of a predetermined number of predetermined lengths. The decoding logic is further configured to form basic blocks of instructions from the padded and decoded instructions. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. The basic block cache is configured to store the basic blocks in a plurality of storage locations, wherein each storage location is configured to store an address tag, a link bit, and at least a portion of one basic block. The link bit indicates whether the basic block stored in said storage location extends into another storage location. The branch prediction unit has a branch prediction array storing branch prediction information corresponding to each storage location within the basic block cache. A computer system and method for operating are also disclosed.
摘要翻译： 公开了一种配置成缓存基本指令块的微处理器。 微处理器可以包括解码逻辑，基本块高速缓存和分支预测单元。 解码逻辑被耦合以将可变长度指令接收和解码为具有预定数量的预定长度之一的填充指令。 解码逻辑还被配置为从填充和解码的指令形成指令的基本块。 基本块是由分支指令产生的指令流中的自然分割。 基本块的开始是分支的目标，而结束是另一个分支指令。 基本块高速缓存被配置为将基本块存储在多个存储位置中，其中每个存储位置被配置为存储地址标签，链接位和一个基本块的至少一部分。 链接位指示存储在所述存储位置中的基本块是否延伸到另一个存储位置。 分支预测单元具有分支预测阵列，其存储与基本块高速缓存内的每个存储位置相对应的分支预测信息。 还公开了一种用于操作的计算机系统和方法。
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