发明授权
US06406962B1 Vertical trench-formed dual-gate FET device structure and method for creation
失效
垂直沟槽形双栅FET器件结构及其制作方法
- 专利标题: Vertical trench-formed dual-gate FET device structure and method for creation
- 专利标题(中): 垂直沟槽形双栅FET器件结构及其制作方法
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申请号: US09761931申请日: 2001-01-17
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公开(公告)号: US06406962B1公开(公告)日: 2002-06-18
- 发明人: Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
- 申请人: Paul D. Agnello , Arne W. Ballantine , Ramachandra Divakaruni , Erin C. Jones , Edward J. Nowak , Jed H. Rankin
- 主分类号: H01L21336
- IPC分类号: H01L21336
摘要:
The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.
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