公开(公告)号：US06406962B1

公开(公告)日：2002-06-18

申请号：US09761931

申请日：2001-01-17

申请人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

发明人： Paul D. Agnello ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Erin C. Jones ,  Edward J. Nowak ,  Jed H. Rankin

IPC分类号： H01L21336

CPC分类号： H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/78642

摘要： The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

摘要翻译： 本发明涉及一种形成具有垂直沟槽形成的双栅极的一个或多个FET的装置和方法，其中多个氮化物层具有周期性地设置在其上的氧化物标记蚀刻停止层，从而使FET具有 多个可选择的栅极长度。 本发明提供控制和形成尺寸缩小到约5nm至约100nm，优选约5nm至约50nm的栅极长度。 具有氧化物蚀刻停止层的多个衬垫氮化物层通过蚀刻衬垫氮化物层中的多个通孔来提供本FET连接到具有对应于所使用的栅极长度的各种连接深度的多个触点 由此这些通孔在选定的蚀刻停止层处停止以提供适于与所选择的这些触点连接的通孔。 附加的栅极材料可以沉积在所选择的多个氮化物层的顶表面上，以允许与任何给定FET的栅电极的接触。

公开(公告)号：US06797553B2

公开(公告)日：2004-09-28

申请号：US10205143

申请日：2002-07-24

申请人： James W Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

发明人： James W Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

IPC分类号： H01L218238

CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

公开(公告)号：US06448590B1

公开(公告)日：2002-09-10

申请号：US09695199

申请日：2000-10-24

申请人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

发明人： James W. Adkisson ,  Arne W. Ballantine ,  Ramachandra Divakaruni ,  Jeffrey B. Johnson ,  Erin C. Jones ,  Hon-Sum P. Wong

IPC分类号： H01L2710

CPC分类号： H01L29/4916 ,  H01L21/82345 ,  H01L29/4238 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66666 ,  H01L29/7827

摘要： A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pattern so that each gate material is adjacent to other gate materials. A patterned linear array embodiment is developed for a multiple threshold voltage design. The method of forming a multiple threshold voltage FET requires disposing different gate materials in aligned trenches within a semiconductor wafer, wherein each gate material represents a separate work function. The gate materials are arranged to be in close proximity to one another to accommodate small gate length designs.

摘要翻译： 通过提供具有多个阈值电压的晶片来实现用于非常大规模集成电路芯片的较短栅长FET。 通过组合多个功能门极材料来开发多个阈值电压。 栅极材料以预定图案几何对准，使得每个栅极材料与其它栅极材料相邻。 开发了用于多阈值电压设计的图案化线性阵列实施例。 形成多阈值电压FET的方法需要在半导体晶片内的对准沟槽中布置不同的栅极材料，其中每个栅极材料表示单独的功函数。 栅极材料被布置成彼此靠近以适应小栅极长度设计。

公开(公告)号：US06429101B1

公开(公告)日：2002-08-06

申请号：US09240753

申请日：1999-01-29

申请人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

发明人： Ricky S. Amos ,  Arne W. Ballantine ,  Gregory Bazan ,  Bomy A. Chen ,  Douglas D. Coolbaugh ,  Ramachandra Divakaruni ,  Heidi L. Greer ,  Herbert L. Ho ,  Joseph F. Kudlacik ,  Bernard P. Leroy ,  Paul C. Parries ,  Gary L. Patton

IPC分类号： H01L2120

CPC分类号： H01L21/02126 ,  H01L21/0214 ,  H01L21/02236 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/31662

摘要： A method for forming a thermally stable ohmic contact structure that includes a region of monocrystalline semiconductor and a region of polycrystalline semiconductor. At least one region of dielectric material is formed between at least a portion of the region of monocrystalline semiconductor and the region of polycrystalline semiconductor, thereby controlling grain growth of the polycrystalline semiconductor.

摘要翻译： 一种形成包含单晶半导体区域和多晶半导体区域的热稳定欧姆接触结构的方法。 在单晶半导体区域的至少一部分与多晶半导体区域之间形成介电材料的至少一个区域，从而控制多晶半导体的晶粒生长。

公开(公告)号：US06686617B2

公开(公告)日：2004-02-03

申请号：US09878804

申请日：2001-06-11

申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

IPC分类号： H01L27108

CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

公开(公告)号：US06287913B1

公开(公告)日：2001-09-11

申请号：US09427506

申请日：1999-10-26

申请人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

发明人： Paul D. Agnello ,  Bomy A. Chen ,  Scott W. Crowder ,  Ramachandra Divakaruni ,  Subramanian S. Iyer ,  Dennis Sinitsky

IPC分类号： H01L218242

CPC分类号： H01L27/10861 ,  H01L21/823443 ,  H01L21/82345 ,  H01L27/10873 ,  H01L27/10894

摘要： A process for fabrication of both compact memory and high performance logic on the same semiconductor chip. The process comprises forming a memory device in the memory region, forming a spacer nitride layer and a protective layer over both the memory region and the logic region, removing the protective layer over the logic region to expose the substrate, and forming the logic device in the logic region. Cobalt or titanium metal is applied over all horizontal surfaces in the logic region and annealed, forming a salicide where the metal rests over silicon or polysilicon regions, and any unreacted metal is removed. An uppermost nitride layer is then applied over both the memory and logic regions and is then covered with a filler in the logic region. Chip structures resulting from various embodiments of the process are also disclosed.

摘要翻译： 在同一半导体芯片上制造紧凑型存储器和高性能逻辑的工艺。 该过程包括在存储器区域中形成存储器件，在存储区域和逻辑区域两者之间形成间隔氮化物层和保护层，去除逻辑区域上的保护层以暴露衬底，以及形成逻辑器件 逻辑区域。 将钴或钛金属施加在逻辑区域的所有水平表面上并退火，形成硅化物，其中金属沉积在硅或多晶硅区域上，并且任何未反应的金属被去除。 然后将最上面的氮化物层施加在存储器和逻辑区域两者上，然后在逻辑区域中用填料覆盖。 还公开了由该方法的各种实施方案产生的芯片结构。

公开(公告)号：US09515140B2

公开(公告)日：2016-12-06

申请号：US12015272

申请日：2008-01-16

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L29/73 ,  H01L29/10 ,  H01L29/739 ,  H01L29/786 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/823412 ,  H01L29/739 ,  H01L29/78687

摘要： A method that includes forming a pattern of strained material and relaxed material on a substrate; forming a strained device in the strained material; and forming a non-strained device in the relaxed material is disclosed. In one embodiment, the strained material is silicon (Si) in either a tensile or compressive state, and the relaxed material is Si in a normal state. A buffer layer of silicon germanium (SiGe), silicon carbon (SiC), or similar material is formed on the substrate and has a lattice constant/structure mis-match with the substrate. A relaxed layer of SiGe, SiC, or similar material is formed on the buffer layer and places the strained material in the tensile or compressive state. In another embodiment, carbon-doped silicon or germanium-doped silicon is used to form the strained material. The structure includes a multi-layered substrate having strained and non-strained materials patterned thereon.

摘要翻译： 一种包括在基板上形成应变材料和松弛材料的图案的方法; 在应变材料中形成应变装置; 并且公开了在松弛材料中形成非应变装置。 在一个实施例中，应变材料是处于拉伸或压缩状态的硅（Si），松弛材料是处于正常状态的Si。 在衬底上形成硅锗（SiGe），硅碳（SiC）或类似材料的缓冲层，其晶格常数/结构与衬底失配。 在缓冲层上形成SiGe，SiC或类似材料的松散层，并将应变材料置于拉伸或压缩状态。 在另一个实施例中，使用掺碳硅或锗掺杂硅来形成应变材料。 该结构包括具有图案化的应变和非应变材料的多层基底。

公开(公告)号：US08703552B2

公开(公告)日：2014-04-22

申请号：US13419624

申请日：2012-03-14

申请人： Kangguo Cheng ,  Ramachandra Divakaruni

发明人： Kangguo Cheng ,  Ramachandra Divakaruni

IPC分类号： H01L27/06 ,  H01L21/8242

CPC分类号： H01L21/84 ,  H01L27/0207 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/66181

摘要： A device is provided that includes memory, logic and capacitor structures on a semiconductor-on-insulator (SOI) substrate. In one embodiment, the device includes a semiconductor-on-insulator (SOI) substrate having a memory region and a logic region. Trench capacitors are present in the memory region and the logic region, wherein each of the trench capacitors is structurally identical. A first transistor is present in the memory region in electrical communication with a first electrode of at least one trench capacitor that is present in the memory region. A second transistor is present in the logic region that is physically separated from the trench capacitors by insulating material. In some embodiments, the trench capacitors that are present in the logic region include decoupling capacitors and inactive capacitors. A method for forming the aforementioned device is also provided.

摘要翻译： 提供了一种在绝缘体上半导体（SOI）衬底上包括存储器，逻辑和电容器结构的器件。 在一个实施例中，该器件包括具有存储区域和逻辑区域的绝缘体上半导体（SOI）衬底。 沟槽电容器存在于存储器区域和逻辑区域中，其中每个沟槽电容器在结构上相同。 第一晶体管存在于与存在于存储器区域中的至少一个沟槽电容器的第一电极电连通的存储区域中。 第二晶体管存在于通过绝缘材料与沟槽电容器物理分离的逻辑区域中。 在一些实施例中，存在于逻辑区域中的沟槽电容器包括去耦电容器和无效电容器。 还提供了一种用于形成上述装置的方法。

公开(公告)号：US08492818B2

公开(公告)日：2013-07-23

申请号：US12881481

申请日：2010-09-14

申请人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

发明人： Keith Kwong Hon Wong ,  Ramachandra Divakaruni ,  Roger A. Booth, Jr.

IPC分类号： H01L27/108

CPC分类号： H01L28/40 ,  H01L27/10861 ,  H01L27/10867 ,  H01L29/945

摘要： A dual node dielectric trench capacitor includes a stack of layers formed in a trench. The stack of layers include, from bottom to top, a first conductive layer, a first node dielectric layer, a second conductive layer, a second node dielectric layer, and a third conductive layer. The dual node dielectric trench capacitor includes two back-to-back capacitors, which include a first capacitor and a second capacitor. The first capacitor includes the first conductive layer, the first node dielectric layer, the second conductive layer, and the second capacitor includes the second conductive layer, the second node dielectric layer, and the third conductive layer. The dual node dielectric trench capacitor can provide about twice the capacitance of a trench capacitor employing a single node dielectric layer having a comparable composition and thickness as the first and second node dielectric layers.

摘要翻译： 双节点介质沟槽电容器包括在沟槽中形成的一叠层。 层的堆叠包括从底部到顶部的第一导电层，第一节点电介质层，第二导电层，第二节点电介质层和第三导电层。 双节点介电沟槽电容器包括两个背对背电容器，其包括第一电容器和第二电容器。 第一电容器包括第一导电层，第一节点电介质层，第二导电层，第二电容器包括第二导电层，第二节点电介质层和第三导电层。 双节点介质沟槽电容器可以提供使用具有与第一和第二节点电介质层相当的组成和厚度的单节点电介质层的沟槽电容器的大约两倍的电容。

公开(公告)号：US20120256267A1

公开(公告)日：2012-10-11

申请号：US13080019

申请日：2011-04-05

申请人： Ying Li ,  Ramachandra Divakaruni

发明人： Ying Li ,  Ramachandra Divakaruni

IPC分类号： H01L27/06 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L23/5256 ,  H01L27/0629 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for fabricating an electrical fuse and a field effect transistor having a metal gate which includes removing material from first and second openings in a dielectric region overlying a substrate, wherein the first opening is aligned with an active semiconductor region of the substrate, and the second opening is aligned with an isolation region of the substrate, and the active semiconductor region including a source region and a drain region adjacent edges of the first opening. An electrical fuse can be formed which has a fuse element filling the second opening, the fuse element being a monolithic region of a single conductive material being a metal or a conductive compound of a metal. A metal gate can be formed which extends within the first opening to define a field effect transistor (“FET”) which includes the metal gate and the active semiconductor region.

摘要翻译： 提供一种用于制造电熔丝和场效应晶体管的方法，所述场效应晶体管具有金属栅极，该金属栅极包括从覆盖衬底的电介质区域中的第一和第二开口去除材料，其中第一开口与衬底的有源半导体区域对准， 并且所述第二开口与所述衬底的隔离区域对准，并且所述有源半导体区域包括与所述第一开口的边缘相邻的源极区域和漏极区域。 可以形成电熔丝，其具有填充第二开口的熔丝元件，熔丝元件是单一导电材料的整体区域，金属或金属的导电化合物。 可以形成在第一开口内延伸的金属栅极，以限定包括金属栅极和有源半导体区域的场效应晶体管（FET）。