A ferroelectric memory device including a single ferroelectric transistor that one unit memory cell is independently selected and programmed, when the unit memory cell is programmed for “the first state” or “the second state” by applying a DC bias voltage to the single ferroelectric transistor's gate and well. In addition, the ferroelectric memory device can be applied with normal power level Vdd and GND. The ferroelectric memory device includes a plurality of unit memory cells which are arranged in a matrix, by crossing at least one word line in a column direction with a plurality of bit lines and source lines in a row direction and is connected between the source line and the bit line.