发明授权
US06411660B1 Device for reducing lock-up time of Frequency synthesizer 失效
减少频率合成器锁定时间的装置

  • 专利标题: Device for reducing lock-up time of Frequency synthesizer
  • 专利标题(中): 减少频率合成器锁定时间的装置
  • 申请号: US09080518
    申请日: 1998-05-18
  • 公开(公告)号: US06411660B1
    公开(公告)日: 2002-06-25
  • 发明人: Tae-won Oh
  • 申请人: Tae-won Oh
  • 优先权: KR97/18906 19970516
  • 主分类号: H03D318
  • IPC分类号: H03D318
Device for reducing lock-up time of Frequency synthesizer
摘要:
A device for reducing a lock-up time in a digital cordless telephone. The telephone includes a first frequency synthesizer for generating a reference frequency, a receiver having a first mixer for mixing the reference frequency with an input frequency to generate a first intermediate frequency and a second mixer to generate a second intermediate frequency, and a transmitter having a third mixer to generate a transmission frequency. The device includes: a band switching controller for receiving an inverse channel selection signal; and a second frequency synthesizer for generating third and fourth intermediate frequencies to the second and third mixers, respectively, according to a channel selection signal for setting transmission and reception modes. The second frequency synthesizer includes: a voltage controlled oscillator for generating a frequency according to a charge pump voltage applied at an input of the oscillator; a loop filter for shaping the charge pump voltage being applied to the input of the voltage controlled oscillator; and a phase locked loop for comparing the reference frequency with a frequency output from the voltage controlled oscillator to generate a voltage according to a phase difference therebetween to the input of the voltage controlled oscillator via the loop filter. The band switching controller maintains an input voltage of the voltage controlled oscillator upon receiving the inverse channel selection signal.
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