公开(公告)号：US06785346B1

公开(公告)日：2004-08-31

申请号：US09676233

申请日：2000-09-29

申请人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

发明人： Neil Birkett ,  Norm Filiol ,  Thomas Riley

IPC分类号： H03D318

CPC分类号： H04L27/3836 ,  H03D3/245

摘要： A digital demodulator which coherently demodulates a low-IF or zero-IF complex signal using a complex-valued phase-locked loop (CPPL). The CPPL includes a numerical controlled oscillator, four multipliers and two combiners to provide independent phase/frequency and amplitude outputs. The CPLL exhibits in first order PLL dynamics without a loop filter in the feedback loop to the NCO. However a filter with one or more poles may be included in the feedback circuit to exhibit 2nd or higher order PLL dynamics. The CPLL allows coherent demodulation of extremely low FM modulation indexes whereby the incoming frequency drift may be larger than the frequency deviation. It can also be used to coherently demodulate signals which have combined amplitude and phase characteristics.

摘要翻译： 数字解调器，其使用复值锁相环（CPPL）相干地解调低中频或零中频复信号。 CPPL包括数控振荡器，四个乘法器和两个组合器，以提供独立的相位/频率和幅度输出。 CPLL在没有环路滤波器的一阶PLL动态中展现了到NCO的反馈环路。 然而，具有一个或多个极点的滤波器可以包括在反馈电路中以呈现2阶或更高阶PLL动力学。 CPLL允许相干解调极低的FM调制指数，从而输入频率漂移可能大于频率偏差。 它也可以用于相干解调具有组合幅度和相位特性的信号。

公开(公告)号：US06295325B1

公开(公告)日：2001-09-25

申请号：US09114949

申请日：1998-07-14

申请人： Cecil William Farrow ,  Daniel J. Udovic ,  Vahid Marandi ,  Mohammad Shafiul Mobin ,  Kaylan Mondal ,  Kai-Chuen Wong

发明人： Cecil William Farrow ,  Daniel J. Udovic ,  Vahid Marandi ,  Mohammad Shafiul Mobin ,  Kaylan Mondal ,  Kai-Chuen Wong

IPC分类号： H03D318

CPC分类号： H04L7/0278 ,  H04L7/0004 ,  H04L7/0025 ,  H04L7/0029

摘要： A QAM data signal timing recovery loop feedback element provides a fixed sampling time offset adjustment to two continuously variable digital rate interpolators/decimators to produce a quadrature output stream at a programmed rational rate multiple of the actual baud rate of the received data signal. The continuously variable digital rate interpolators/decimators are configured at startup so as to produce output streams at the same programmed rational rate multiple of the nominal baud rate of the anticipated received data signal, assuming the fs sample timing offset adjustment stream provided by the timing recovery feedback element to be identically 0. The “nominal” fixed sampling rate fs of the received analog input signal need not be rationally related to the nominal baud rate of the anticipated received data signal.

摘要翻译： QAM数据信号定时恢复环路反馈元件提供对两个连续可变数字速率内插器/抽取器的固定采样时间偏移调整，以按接收数据信号的实际波特率的编程有理速率倍数产生正交输出流。 假设由定时恢复提供的fs采样定时偏移调整流，启动时配置连续可变数字速率内插器/抽取器，以便产生与预期接收数据信号的额定波特率相同的编程有理数倍的输出流 反馈元件相同为0.接收的模拟输入信号的“额定”固定采样率fs不需要与预期接收数据信号的标称波特率合理相关。

公开(公告)号：US06236688B1

公开(公告)日：2001-05-22

申请号：US09258402

申请日：1999-02-26

申请人： Gen-ichiro Ohta ,  Kazunori Inogai ,  Fujio Sasaki

发明人： Gen-ichiro Ohta ,  Kazunori Inogai ,  Fujio Sasaki

IPC分类号： H03D318

CPC分类号： H04B1/0032 ,  H03D1/2245 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0082 ,  H03F3/45475 ,  H03F3/50 ,  H03F2200/537 ,  H04B1/0003 ,  H04B1/123 ,  H04B1/26 ,  H04B5/0093 ,  Y02D70/40 ,  Y02D70/42

摘要： A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of &ohgr;o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8. In addition, the common wave extracting circuit 5 has transformers and, using its inductances, raises the difference between the common wave and the non-common wave within the circuit to more than two times that of a prior art.

摘要翻译： 主要可用于具有多个信道的数字调制型通信系统中的接收电路，其能够降低接收系统的功率，简化电路并降低功耗。 对应于通道之间的中心值的上升和下降频率从本地频率信号发生电路4分别提供给第一和第二频率转换电路2,3，使得两个输出信号相对于所需波形，上行通道 和下行通道。 在公共波提取电路5中提取在第一和第二频率转换电路2,3中共同存在的期望的波，并且公共波提取电路5的输出中存在的ωω的频率偏移被去除频率偏移电路 此外，公共波提取电路5还具有变压器，并且使用其电感将电路内的公共波和非公共波之间的差异提高到超过 是现有技术的两倍。

公开(公告)号：US06771715B1

公开(公告)日：2004-08-03

申请号：US09538673

申请日：2000-03-30

申请人： Eric M. Rives ,  Matthew F. Gann ,  Anthony A. Goodloe

发明人： Eric M. Rives ,  Matthew F. Gann ,  Anthony A. Goodloe

IPC分类号： H03D318

CPC分类号： H04L27/2332 ,  H04L2027/003 ,  H04L2027/0057

摘要： A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.

摘要翻译： 数字数据解调器采用基于旋转器的数字锁相环，用于载波频率跟踪。 使用固定频率振荡器下变频到基带的数字化I和Q通道耦合到数字有线旋转器。 伴随着由数字相位误差检测逻辑电路产生的相位角矢量码的累积值的流水线减少，旋转的I和Q 绳索旋转器的输出被应用。 相位误差代表代码矢量通过数字环路滤波器耦合，作为向心轴旋转器输入的参考角。 电磁旋转器将I和Q通道值迭代地旋转，从而将累积的相位误差减小到零。

公开(公告)号：US06700941B1

公开(公告)日：2004-03-02

申请号：US09536199

申请日：2000-03-27

申请人： Fumiaki Nagao

发明人： Fumiaki Nagao

IPC分类号： H03D318

CPC分类号： H04L25/4904

摘要： A digital demodulation apparatus for performing a stable oscillation operation has a simple circuit configuration. The digital demodulation apparatus includes a pulse width counter for measuring a cycle of a modulated signal to generate digital cycle information. A first digital filter equalizes the digital cycle information to generate averaged cycle information. A comparator compares the digital cycle information and the averaged cycle information to generate a bi-phase signal. A phase-locked loop generates a clock signal having a frequency according to the averaged cycle information and a phase being synchronized with the phase of the bi-phase signal.

摘要翻译： 用于执行稳定振荡操作的数字解调装置具有简单的电路结构。 数字解调装置包括用于测量调制信号的周期以生成数字周期信息的脉冲宽度计数器。 第一数字滤波器均衡数字周期信息以产生平均周期信息。 比较器比较数字周期信息和平均周期信息以产生双相信号。 锁相环产生具有根据平均周期信息的频率的时钟信号，并且相位与双相信号的相位同步。

公开(公告)号：US06516038B1

公开(公告)日：2003-02-04

申请号：US09258419

申请日：1999-02-26

申请人： Gen-ichiro Ohta ,  Kazunori Inogai ,  Fujio Sasaki

发明人： Gen-ichiro Ohta ,  Kazunori Inogai ,  Fujio Sasaki

IPC分类号： H03D318

CPC分类号： H04B1/0032 ,  H03D1/2245 ,  H03D7/165 ,  H03D2200/0047 ,  H03D2200/005 ,  H03D2200/0082 ,  H03F3/45475 ,  H03F3/50 ,  H03F2200/537 ,  H04B1/0003 ,  H04B1/123 ,  H04B1/26 ,  H04B5/0093 ,  Y02D70/40 ,  Y02D70/42

摘要： A receiving circuit mainly available in a digital modulation type communication system having a plurality of channels, which is capable of reducing power in a receiving system, simplifying the circuit and reducing the power consumption. Upside and downside frequencies corresponding to a central value between channels are separately supplied from a local frequency signal generating circuit 4 to first and second frequency converting circuits 2, 3 so that two output signals are developed with respect to one of a desired wave, upside channel and downside channel. The desired wave present in common in the first and second frequency converting circuits 2, 3 is extracted in a common wave extracting circuit 5, and a frequency offset of &ohgr;o existing in the output of the common wave extracting circuit 5 is removed a frequency offset circuit 6 and further an unnecessary frequency component is filtered by a filter 8. In addition, the common wave extracting circuit 5 has transformers and, using its inductances, raises the difference between the common wave and the non-common wave within the circuit to more than two times that of a prior art.

摘要翻译： 主要可用于具有多个信道的数字调制型通信系统中的接收电路，其能够降低接收系统的功率，简化电路并降低功耗。 对应于通道之间的中心值的上升和下降频率从本地频率信号发生电路4分别提供给第一和第二频率转换电路2,3，使得两个输出信号相对于所需波形，上行通道 和下行通道。 在公共波提取电路5中提取在第一和第二频率转换电路2,3中共同存在的期望的波，并且公共波提取电路5的输出中存在的ωω的频率偏移被去除频率偏移电路 此外，公共波提取电路5还具有变压器，并且使用其电感将电路内的公共波和非公共波之间的差异提高到超过 是现有技术的两倍。

公开(公告)号：US06473470B1

公开(公告)日：2002-10-29

申请号：US09309830

申请日：1999-05-11

申请人： Hitosi Matui

发明人： Hitosi Matui

IPC分类号： H03D318

CPC分类号： H04L27/0014 ,  H04L25/03273 ,  H04L2027/0071

摘要： In a phase-locked loop circuit with a signal estimator such as MLSE or DDFSE for correctly detecting and correcting a phase deviation, the phase deviation is held within a predetermined value by amplitude limiting a phase deviation signal obtained from a received signal and a replica signal. Thus, the phase deviation signal is free from a large error irrespective of generation of an estimation error in the MLSE or DDFSE.

摘要翻译： 在具有用于正确检测和校正相位偏差的信号估计器（例如MLSE或DDFSE）的锁相环电路中，相位偏差通过幅度限制从接收信号和复制信号获得的相位偏差信号而保持在预定值内 。 因此，与MLSE或DDFSE中的估计误差的生成无关，相位偏差信号没有大的误差。

公开(公告)号：US06807237B1

公开(公告)日：2004-10-19

申请号：US09701697

申请日：2000-12-01

申请人： Manabu Yamaguchi ,  Toshio Obara

发明人： Manabu Yamaguchi ,  Toshio Obara

IPC分类号： H03D318

CPC分类号： H04B1/406 ,  H04B1/00 ,  H04B1/403 ,  H04B1/44

摘要： At the time of ordinary communication, up-mixer 108 combines a signal with a frequency f2 from frequency synthesizer 124 with I and Q signals for transmission that are quadrature modulated in quadrature modulator 105, down-mixer 115 combines the signal with the frequency f2 with a received signal, then only in the case of receiving a signal with a frequency fr′ different from a frequency fr, frequency synthesizer 125 that generates a signal with a frequency f3 different from the frequency f2 is operated, and frequency synthesizer 125 and down-mixer 115 are connected with switch 127, so that down-mixer 115 combines the signal with the frequency f3 with a received signal. It is thereby possible to switch frequencies fast and with low current consumption in receiving a signal with a reception frequency other than a combination of transmission frequency and reception frequency specified in an ordinary radio system.

摘要翻译： 在通常通信时，上混频器108将来自频率合成器124的信号与来自频率合成器124的频率f2的信号和正交调制器105正交调制的I和Q信号组合在一起，下混频器115将信号与频率f2组合在一起， 接收信号，则只有在接收到频率fr'不同于频率fr的信号的情况下，才产生频率合成器125，频率合成器125产生频率f3不同于频率f2的频率，频率合成器125和下行频率合成器125， 混频器115与开关127连接，使得下混频器115将信号与频率f3组合成接收信号。 从而可以在以普通无线电系统中指定的发送频率和接收频率的组合以外的接收频率接收信号时，快速地切换频率并且具有低电流消耗。

公开(公告)号：US06639952B1

公开(公告)日：2003-10-28

申请号：US09333351

申请日：1999-06-15

申请人： Jacques Meyer

发明人： Jacques Meyer

IPC分类号： H03D318

CPC分类号： H04L27/2273 ,  H04L2027/003 ,  H04L2027/0053

摘要： A method for detecting the lock-in of a loop that synchronizes an internal clock on the transmission of value pairs provided by a demodulator. According to the method, a module of a vector that has as components the values of one of the value pairs is calculated, and the module is compared with a threshold that is smaller than a theoretical module. The locked-in condition is determined according to the ratio of the number of modules found to be greater than or smaller than the threshold to the total number of modules. In one preferred method, the threshold is incremented by a first value if the module is greater than the threshold and is decremented by a second value if the module is less than the threshold. A lock-in detection circuit for detecting the lock-in of a loop is also provided. A calculation circuit calculates a module of a vector that has as components the values of one of the value pairs. A register stores a threshold and a comparator compares the stored threshold with the calculated module. A modification circuit modifies the stored threshold based on the comparison result, and an analysis circuit analyzes the stored threshold to determine the locked-in condition.

摘要翻译： 一种用于检测在由解调器提供的值对的传输上同步内部时钟的环路的锁定的方法。 根据该方法，计算具有作为值对之一的值的分量的向量的模块，并将模块与小于理论模块的阈值进行比较。 锁定状态根据发现大于或小于阈值的模块数与模块总数之比确定。 在一个优选方法中，如果模块大于阈值，则阈值增加第一值，并且如果模块小于阈值则递减第二值。 还提供了用于检测环路锁定的锁定检测电路。 计算电路计算具有作为值对之一的值的分量的向量的模块。 寄存器存储阈值，比较器将存储的阈值与计算出的模块进行比较。 修改电路根据比较结果修改存储的阈值，并且分析电路分析存储的阈值以确定锁定状态。

公开(公告)号：US06466630B1

公开(公告)日：2002-10-15

申请号：US09246214

申请日：1999-01-27

申请人： James Robert Jensen

发明人： James Robert Jensen

IPC分类号： H03D318

CPC分类号： H04L27/2332 ,  H03J7/04 ,  H04L7/0334

摘要： Symbol synchronization in a continuous phase modulation receiver is achieved by calculating an arctangent function of a digital sample of the output of a quadrature demodulator. This signal is sampled by integration techniques or filtered to produce signals that represent a complex value whose phase changes at a rate which is half of the symbol rate. The complex value may be squared and rotated by an angle which is related to the symbol phase. The integrated sample or an arctangent function of the filtered sample is used as a controlling input for a numerically controlled oscillator which regulates the digital sampling.

摘要翻译： 通过计算正交解调器的输出的数字样本的反正切函数来实现连续相位调制接收器中的符号同步。 该信号通过积分技术进行采样或被滤波以产生表示复数值的信号，其相位以符号率的一半的速率改变。 复数值可以被平方并旋转与符号相位相关的角度。 滤波样本的积分样本或反正切函数用作调节数字采样的数控振荡器的控制输入。