发明授权
- 专利标题： Process for reduction of capacitance of a bitline for a non-volatile memory cell
- 专利标题（中）： 降低非易失性存储单元的位线电容的工艺
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申请号： US09721066申请日： 2000-11-22
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公开(公告)号： US06417081B1公开(公告)日： 2002-07-09
- 发明人: Timothy J. Thurgate
- 申请人： Timothy J. Thurgate
- 主分类号： H01L21425
- IPC分类号： H01L21425
摘要：
A process for forming an array of memory cells that includes forming a buried bitline region by implanting an n-type dopant in a region of a semiconductor substrate, wherein there is a severe differential change going from the bitline region to the substrate region causing the capacitance of a junction between the bitline region and the semiconductor to be large and reducing the capacitance of the junction.
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