公开(公告)号：US06759314B1

公开(公告)日：2004-07-06

申请号：US09670520

申请日：2000-09-26

申请人： Wakako Moriyama ,  Naoki Kai ,  Hiroaki Hazama ,  Keiki Nagai ,  Yuji Fukazawa ,  Kazuo Saki ,  Yoshio Ozawa ,  Yasumasa Suizu

发明人： Wakako Moriyama ,  Naoki Kai ,  Hiroaki Hazama ,  Keiki Nagai ,  Yuji Fukazawa ,  Kazuo Saki ,  Yoshio Ozawa ,  Yasumasa Suizu

IPC分类号： H01L21425

CPC分类号： H01L21/28202 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28273 ,  H01L21/31662 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/511 ,  H01L29/518

摘要： A thermal nitride film is formed as a gate insulating film on a silicon substrate, and after a gate electrode material is formed on the insulating film, it is patterned to form gate electrodes. After processing the electrodes, part of the gate insulating film other than a portion thereof which lies under the gate electrodes is removed. Further, an insulating film (a post oxidation film) is formed on side walls and upper surfaces of the stacked gate structures and the exposed main surface of the silicon substrate by use of thermal oxidation method.

摘要翻译： 在硅衬底上形成作为栅极绝缘膜的热氮化膜，在绝缘膜上形成栅极电极材料之后，形成栅电极。 在处理电极之后，除去位于栅电极下方的栅极绝缘膜的除了其一部分之外的部分。 此外，通过使用热氧化法在堆叠的栅极结构的侧壁和上表面以及硅衬底的暴露的主表面上形成绝缘膜（后氧化膜）。

公开(公告)号：US06667226B2

公开(公告)日：2003-12-23

申请号：US10024091

申请日：2001-12-14

申请人： Angelo Pinto ,  Ricardo A. Romani ,  Gregory E. Howard

发明人： Angelo Pinto ,  Ricardo A. Romani ,  Gregory E. Howard

IPC分类号： H01L21425

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A semiconductor device and a method for constructing a semiconductor device is disclosed. A deep trench isolation structure (108) is formed proximate a surface of a semiconductor substrate (106). A deep trench plug (122) layer is deposited within the deep trench isolation structure (108). A shallow trench isolation structure (130) is formed where the deep trench isolation structure (108) meets the surface of the semiconductor substrate (106). A shallow trench plug layer (133) is deposited within the shallow trench isolation structure (130).

公开(公告)号：US06645837B2

公开(公告)日：2003-11-11

申请号：US09871033

申请日：2001-05-31

申请人： Dharam Pal Gosain ,  Kazumasa Nomoto ,  Akio Machida ,  Miyako Nakagoe ,  Setsuo Usui

发明人： Dharam Pal Gosain ,  Kazumasa Nomoto ,  Akio Machida ,  Miyako Nakagoe ,  Setsuo Usui

IPC分类号： H01L21425

CPC分类号： H01L29/66757 ,  H01L27/12

摘要： A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.

公开(公告)号：US06632727B2

公开(公告)日：2003-10-14

申请号：US09939900

申请日：2001-08-27

申请人： Howard E. Rhodes ,  Kirk D. Prall ,  Philip J. Ireland ,  Kenneth N. Hagen

发明人： Howard E. Rhodes ,  Kirk D. Prall ,  Philip J. Ireland ,  Kenneth N. Hagen

IPC分类号： H01L21425

CPC分类号： H01L21/26586 ,  H01L21/28518

摘要： A method of forming electrical contacts includes the step of implanting ions into a contact hole at an angle to create an enlarged plug enhancement region at the bottom of a contact hole. Thus, even if the contact hole is misaligned, over-sized, or over-etched, the enlarged plug enhancement region contains subsequently formed barrier layers and other conductive materials to reduce current leakage into the underlying substrate or into adjacent circuit elements.

摘要翻译： 形成电触点的方法包括以一定角度将离子注入接触孔中以在接触孔的底部产生扩大的插塞增强区域的步骤。 因此，即使接触孔不对准，过大或过度蚀刻，扩大的插塞增强区域随后形成阻挡层和其他导电材料，以减少电流泄漏到下面的衬底或相邻的电路元件中。 >

公开(公告)号：US06548381B2

公开(公告)日：2003-04-15

申请号：US10131085

申请日：2002-04-25

申请人： Nariaki Hamamoto

发明人： Nariaki Hamamoto

IPC分类号： H01L21425

CPC分类号： H01J37/317 ,  H01J2237/0041 ,  H01L21/2236

摘要： When a plasma is ignited in a plasma generator, an ion beam is made to run in the plasma generator, and in this state, a positive voltage with respective to ground is applied to a plasma production chamber from a DC power source. Secondary electrons are generated when the ion beam collides with a plasma generating gas which flows out of the plasma production chamber into a path of the ion beam. The secondary electrons are led into the plasma production chamber by the positive voltage, and within the plasma production chamber, a plasma ignition is triggered using the secondary electrons led into the plasma production chamber and a radio frequency.

公开(公告)号：US06489223B1

公开(公告)日：2002-12-03

申请号：US09898949

申请日：2001-07-03

申请人： Terence B. Hook ,  Randy W. Mann

发明人： Terence B. Hook ,  Randy W. Mann

IPC分类号： H01L21425

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/66659 ,  H01L29/7835

摘要： Different symmetrical and asymmetrical devices are formed on the same chip using non-critical block masks and angled implants. A barrier is selectively formed adjacent one side of a structure and this barrier blocks dopant implanted at an angle toward the structure. Other structures have no barrier or have two barriers. Source and drain engineering can be performed for LDD, halo, and other desired implants.

摘要翻译： 不同的对称和非对称装置在同一芯片上使用非关键块掩模和成角度的植入物形成。 选择性地在结构的一侧形成势垒，并且该势垒阻挡以一定角度朝向该结构注入的掺杂剂。 其他结构没有障碍或有两个障碍。 可以对LDD，光晕和其他所需的植入物进行源和漏极工程。

公开(公告)号：US06479372B1

公开(公告)日：2002-11-12

申请号：US09690520

申请日：2000-10-17

申请人： Jimmy Liou ,  Ching-Fang Chu

发明人： Jimmy Liou ,  Ching-Fang Chu

IPC分类号： H01L21425

CPC分类号： H01L21/31111 ,  H01L21/266 ,  Y10S438/906

摘要： A method for forming a hydrophilic surface on a silicon substrate during cleaning step after well implantation comprises providing a silicon substrate and an insulating layer is deposited thereon for mask alignment requirement. A photoresist layer is formed on the insulating layer and then a well pattern is transferred into the photoresist layer to expose partial the insulating layer thereunder the well defined. Next, implants are implanted into the photoresist layer, the insulating layer and the silicon substrate. Then the insulating layer exposed by the photoresist layer is removed and in-situ a native oxide is formed on the silicon substrate thereunder the well defined whereby changes the surface of the silicon substrate from hydrophobic into hydrophilic. A hard skin on the photoresist layer, resulting from implantation, is removed by oxygen plasma ashing and then the surface of the insulating layer and the silicon substrate are cleaned by conventional technologies.

摘要翻译： 在完成注入之后的清洁步骤期间在硅衬底上形成亲水表面的方法包括提供硅衬底，并且在其上沉积绝缘层以进行掩模对准要求。 在绝缘层上形成光致抗蚀剂层，然后将阱图案转移到光致抗蚀剂层中以暴露部分绝缘层在其上限定的绝缘层。 接下来，将注入植入光致抗蚀剂层，绝缘层和硅衬底。 然后去除由光致抗蚀剂层暴露的绝缘层，并且原位氧化物在其上定义的硅衬底上形成，由此将硅衬底的表面从疏水性变为亲水性。 通过氧等离子体灰化除去由注入产生的光致抗蚀剂层上的硬皮，然后通过常规技术清洁绝缘层和硅衬底的表面。

公开(公告)号：US06455402B2

公开(公告)日：2002-09-24

申请号：US09811590

申请日：2001-03-20

申请人： Joo-Hyong Lee ,  Jeong-Hwan Son

发明人： Joo-Hyong Lee ,  Jeong-Hwan Son

IPC分类号： H01L21425

CPC分类号： H01L21/823892 ,  Y10S438/919

摘要： The method of fabricating a semiconductor device includes the steps of selectively forming an insulating oxide layer in a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate has first and second regions; forming impurity layers having a second conductivity type in the first and second regions of the semiconductor substrate; forming a first mask layer in the second region of the semiconductor substrate; forming impurity layers having the second conductivity type in the first region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies; forming a second mask layer in the first region of the semiconductor substrate; and forming impurity layers having the first conductivity type in the second region of the semiconductor substrate by performing serial ion implantations with different doses of dopants at different acceleration energies.

摘要翻译： 制造半导体器件的方法包括以下步骤：在具有第一导电类型的半导体衬底中选择性地形成绝缘氧化物层，其中半导体衬底具有第一和第二区域; 在半导体衬底的第一和第二区域中形成具有第二导电类型的杂质层; 在所述半导体衬底的第二区域中形成第一掩模层; 通过在不同的加速能量下以不同剂量的掺杂剂进行串联离子注入，在半导体衬底的第一区域中形成具有第二导电类型的杂质层; 在所述半导体衬底的所述第一区域中形成第二掩模层; 以及在不同加速能量下通过不同剂量的掺杂剂进行串联离子注入，在半导体衬底的第二区域中形成具有第一导电类型的杂质层。

公开(公告)号：US06444550B1

公开(公告)日：2002-09-03

申请号：US09640177

申请日：2000-08-17

申请人： Ming-Yin Hao ,  Emi Ishida

发明人： Ming-Yin Hao ,  Emi Ishida

IPC分类号： H01L21425

CPC分类号： H01L29/105 ,  H01L21/268 ,  Y10S438/914

摘要： A semiconductor device having a retrograde channel profile is achieved by forming a retrograde impurity region in the surface portion of a semiconductor substrate, and subsequently forming a semiconductor layer on the retrograde impurity region at a predetermined thickness. The thickness of the semiconductor layer is controlled to localize the retrograde impurity region and its impurity concentration peak at a predetermined depth, thereby reducing the device's susceptibility to “reverse short channel effects.”

摘要翻译： 具有逆行通道轮廓的半导体器件通过在半导体衬底的表面部分中形成逆向杂质区域，随后在逆向杂质区域上以预定厚度形成半导体层来实现。 控制半导体层的厚度以将逆向杂质区域和其杂质浓度峰值定位在预定深度，从而减少器件对“反向短沟道效应”的敏感性。

公开(公告)号：US06436798B2

公开(公告)日：2002-08-20

申请号：US09382146

申请日：1999-08-24

申请人： Kuan-Yu Fu

发明人： Kuan-Yu Fu

IPC分类号： H01L21425

CPC分类号： H01L29/7834 ,  H01L21/28114 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/42376 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66787

摘要： A method of fabricating a MOSFET device with a multiple T-shaped gate has the following steps. A substrate with an active region and a non-active region is provided, wherein the active region has a plurality of trenches, and the non-active region has a plurality shallow trench isolation structures. A thin insulating layer and a conducting layer are formed in the trenches. The conducting layer is defined to form a gate. The device is implanted with first ions. Then, the device is further implanted with second ions by using a mask, wherein the mask expose the trenches of the active region, and the opening of the mask is wider than the trench. The MOSFET device has at least the following structures. There is a substrate with an active region and a non-active region, wherein the active region has a plurality of trenches and the non-active region has a plurality of shallow trench isolation structures. There is a multiple T-shaped gate with a first part and a second part, wherein the first part is formed between two trenches on the substrate and the second part is formed in the trenches of the active region. There is a source/drain region with a shallow doped region and a deep doped region. The multiple T-shaped gate increases the channel width of the MOSFET device and decreases the short channel effect of the high integrity ICs.

摘要翻译： 制造具有多个T形栅极的MOSFET器件的方法具有以下步骤。 提供了具有有源区和非有源区的衬底，其中有源区具有多个沟槽，并且非有源区具有多个浅沟槽隔离结构。 在沟槽中形成薄的绝缘层和导电层。 导电层被定义为形成栅极。 器件植入第一个离子。 然后，通过使用掩模将器件进一步注入第二离子，其中掩模暴露有源区的沟槽，并且掩模的开口比沟槽更宽。 MOSFET器件至少具有以下结构。 存在具有有源区和非有源区的衬底，其中有源区具有多个沟槽，而非有源区具有多个浅沟槽隔离结构。 存在具有第一部分和第二部分的多个T形门，其中第一部分形成在衬底上的两个沟槽之间，并且第二部分形成在有源区域的沟槽中。 存在具有浅掺杂区域和深掺杂区域的源极/漏极区域。 多个T形栅极增加了MOSFET器件的沟道宽度，并降低了高完整性IC的短沟道效应。