发明授权
- 专利标题: Peak hold and calibration circuit
- 专利标题(中): 峰值保持和校准电路
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申请号: US09500098申请日: 2000-02-08
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公开(公告)号: US06429696B1公开(公告)日: 2002-08-06
- 发明人: Cheng-Yung Kao , Wen-Tsao Chen , Yung-Pin Lee
- 申请人: Cheng-Yung Kao , Wen-Tsao Chen , Yung-Pin Lee
- 主分类号: G01R1900
- IPC分类号: G01R1900
摘要:
The present invention generally relates to a peak hold and calibration circuit, and more particularly, to a peak hold and calibration circuit for use in measuring the signals in a digital multi-meter implemented by using an integrated circuit (IC) and a capacitor, wherein said IC is connected to said capacitor; wherein said IC comprises an operational amplifier, and a switching circuit; wherein a first voltage is applied to one input terminal of said operational amplifier and the other input terminal of said operational amplifier is connected to the feedback network while the output terminal of said operational amplifier is connected to said switching circuit; wherein the output of said switching circuit is a second voltage and connected to said capacitor. The peak hold and calibration circuit for use in measuring the signals in a digital multi-meter of the present utilizes only a few components, thus it has lower fabricating cost, higher economic profit, low power-consumption and can solve the problems in that the diode which has short switching time, small parasitic capacitance, and small leakage current is hardly found.