发明授权
US06442074B1 Tailored erase method using higher program VT and higher negative gate erase
有权
使用更高程序VT和更高的负栅极擦除进行定制擦除方法
- 专利标题: Tailored erase method using higher program VT and higher negative gate erase
- 专利标题(中): 使用更高程序VT和更高的负栅极擦除进行定制擦除方法
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申请号: US09795854申请日: 2001-02-28
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公开(公告)号: US06442074B1公开(公告)日: 2002-08-27
- 发明人: Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
- 申请人: Darlene G. Hamilton , Kulachet Tanpairoj , Ravi Sunkavalli , Narbeh Derhacobian
- 主分类号: G11C1604
- IPC分类号: G11C1604
摘要:
A method and system for programming and erasing the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT and an erase pulse that provides a substantially high electric field to each I/O in a sector one at a time. After the first erase pulse, the erase verify routine is performed on all the IO's together. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. This erase pulse that provides a substantially high electric field is selected to erase band to band currents for the entire array that are larger than can be supplied by drain pumps.
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